{
struct ilo_context *ilo = ilo_context(data);
- /* invalidate the pipeline */
- ilo_render_invalidate(ilo->render,
- ILO_RENDER_INVALIDATE_BATCH_BO |
- ILO_RENDER_INVALIDATE_STATE_BO |
- ILO_RENDER_INVALIDATE_KERNEL_BO);
+ /* builder buffers are reallocated */
+ ilo_render_invalidate_builder(ilo->render);
}
static void
break;
}
- ilo->render->invalidate_flags = 0x0;
-
/* sanity check size estimation */
assert(before_space - ilo_cp_space(ilo->cp) <= max_len);
break;
}
- ilo_render_invalidate(ilo->render, ILO_RENDER_INVALIDATE_HW);
+ ilo_render_invalidate_hw(ilo->render);
ilo_render_emit_flush(ilo->render);
break;
}
- render->invalidate_flags = ILO_RENDER_INVALIDATE_ALL;
-
render->workaround_bo = intel_winsys_alloc_buffer(builder->winsys,
"PIPE_CONTROL workaround", 4096, false);
if (!render->workaround_bo) {
sample_position_8x[4 + i].y << (8 * i);
}
+ ilo_render_invalidate_hw(render);
+ ilo_render_invalidate_builder(render);
+
return render;
}
*x = (float) pos[sample_index].x / 16.0f;
*y = (float) pos[sample_index].y / 16.0f;
}
+
+void
+ilo_render_invalidate_hw(struct ilo_render *render)
+{
+ render->hw_ctx_changed = true;
+}
+
+void
+ilo_render_invalidate_builder(struct ilo_render *render)
+{
+ render->batch_bo_changed = true;
+ render->state_bo_changed = true;
+ render->instruction_bo_changed = true;
+
+ /* Kernel flushes everything. Shouldn't we set all bits here? */
+ render->state.current_pipe_control_dw1 = 0;
+}
struct ilo_query;
struct ilo_state_vector;
-enum ilo_render_invalidate_flags {
- ILO_RENDER_INVALIDATE_HW = 1 << 0,
- ILO_RENDER_INVALIDATE_BATCH_BO = 1 << 1,
- ILO_RENDER_INVALIDATE_STATE_BO = 1 << 2,
- ILO_RENDER_INVALIDATE_KERNEL_BO = 1 << 3,
-
- ILO_RENDER_INVALIDATE_ALL = 0xffffffff,
-};
-
enum ilo_render_action {
ILO_RENDER_DRAW,
ILO_RENDER_FLUSH,
const struct ilo_dev_info *dev;
struct ilo_builder *builder;
- uint32_t invalidate_flags;
-
struct intel_bo *workaround_bo;
uint32_t packed_sample_position_1x;
void (*emit_rectlist)(struct ilo_render *render,
const struct ilo_blitter *blitter);
+ bool hw_ctx_changed;
+
+ /*
+ * Any state that involves resources needs to be re-emitted when the
+ * batch bo changed. This is because we do not pin the resources and
+ * their offsets (or existence) may change between batch buffers.
+ */
+ bool batch_bo_changed;
+ bool state_bo_changed;
+ bool instruction_bo_changed;
+
/**
* HW states.
*/
void
ilo_render_destroy(struct ilo_render *render);
-
-static inline void
-ilo_render_invalidate(struct ilo_render *render, uint32_t flags)
-{
- render->invalidate_flags |= flags;
-
- /* Kernel flushes everything. Shouldn't we set all bits here? */
- render->state.current_pipe_control_dw1 = 0;
-}
-
/**
* Estimate the size of an action.
*/
unsigned sample_index,
float *x, float *y);
+void
+ilo_render_invalidate_hw(struct ilo_render *render);
+
+void
+ilo_render_invalidate_builder(struct ilo_render *render);
+
#endif /* ILO_RENDER_H */
int reduced_prim;
- bool hw_ctx_changed;
- bool batch_bo_changed;
- bool state_bo_changed;
- bool kernel_bo_changed;
bool prim_changed;
bool primitive_restart_changed;
};
void
-gen6_draw_prepare(const struct ilo_render *r,
+gen6_draw_prepare(struct ilo_render *r,
const struct ilo_state_vector *ilo,
struct gen6_draw_session *session);
struct gen6_draw_session *session)
{
/* PIPELINE_SELECT */
- if (session->hw_ctx_changed) {
+ if (r->hw_ctx_changed) {
if (ilo_dev_gen(r->dev) == ILO_GEN(6))
gen6_wa_pre_non_pipelined(r);
struct gen6_draw_session *session)
{
/* STATE_SIP */
- if (session->hw_ctx_changed) {
+ if (r->hw_ctx_changed) {
if (ilo_dev_gen(r->dev) == ILO_GEN(6))
gen6_wa_pre_non_pipelined(r);
struct gen6_draw_session *session)
{
/* STATE_BASE_ADDRESS */
- if (session->state_bo_changed || session->kernel_bo_changed ||
- session->batch_bo_changed) {
+ if (r->state_bo_changed || r->instruction_bo_changed ||
+ r->batch_bo_changed) {
if (ilo_dev_gen(r->dev) == ILO_GEN(6))
gen6_wa_pre_non_pipelined(r);
- gen6_state_base_address(r->builder, session->hw_ctx_changed);
+ gen6_state_base_address(r->builder, r->hw_ctx_changed);
/*
* From the Sandy Bridge PRM, volume 1 part 1, page 28:
{
if (ilo_dev_gen(r->dev) >= ILO_GEN(7.5)) {
/* 3DSTATE_INDEX_BUFFER */
- if (DIRTY(IB) || session->batch_bo_changed) {
+ if (DIRTY(IB) || r->batch_bo_changed) {
gen6_3DSTATE_INDEX_BUFFER(r->builder,
&vec->ib, false);
}
else {
/* 3DSTATE_INDEX_BUFFER */
if (DIRTY(IB) || session->primitive_restart_changed ||
- session->batch_bo_changed) {
+ r->batch_bo_changed) {
gen6_3DSTATE_INDEX_BUFFER(r->builder,
&vec->ib, vec->draw->primitive_restart);
}
}
/* 3DSTATE_VERTEX_BUFFERS */
- if (DIRTY(VB) || DIRTY(VE) || session->batch_bo_changed)
+ if (DIRTY(VB) || DIRTY(VE) || r->batch_bo_changed)
gen6_3DSTATE_VERTEX_BUFFERS(r->builder, vec->ve, &vec->vb);
/* 3DSTATE_VERTEX_ELEMENTS */
struct gen6_draw_session *session)
{
/* 3DSTATE_VF_STATISTICS */
- if (session->hw_ctx_changed)
+ if (r->hw_ctx_changed)
gen6_3DSTATE_VF_STATISTICS(r->builder, false);
}
struct gen6_draw_session *session)
{
const bool emit_3dstate_vs = (DIRTY(VS) || DIRTY(SAMPLER_VS) ||
- session->kernel_bo_changed);
+ r->instruction_bo_changed);
const bool emit_3dstate_constant_vs = session->pcb_state_vs_changed;
/*
/* 3DSTATE_GS */
if (DIRTY(GS) || DIRTY(VS) ||
- session->prim_changed || session->kernel_bo_changed) {
+ session->prim_changed || r->instruction_bo_changed) {
const int verts_per_prim = u_vertices_per_prim(session->reduced_prim);
gen6_3DSTATE_GS(r->builder, vec->gs, vec->vs, verts_per_prim);
0, 0, r->state.so_max_vertices,
false);
- if (session->hw_ctx_changed) {
+ if (r->hw_ctx_changed) {
int i;
/*
/* 3DSTATE_WM */
if (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND) || DIRTY(DSA) ||
- DIRTY(RASTERIZER) || session->kernel_bo_changed) {
+ DIRTY(RASTERIZER) || r->instruction_bo_changed) {
const int num_samplers = vec->sampler[PIPE_SHADER_FRAGMENT].count;
const bool dual_blend = vec->blend->dual_blend;
const bool cc_may_kill = (vec->dsa->dw_alpha ||
vec->blend->alpha_to_coverage);
- if (ilo_dev_gen(r->dev) == ILO_GEN(6) && session->hw_ctx_changed)
+ if (ilo_dev_gen(r->dev) == ILO_GEN(6) && r->hw_ctx_changed)
gen6_wa_pre_3dstate_wm_max_threads(r);
gen6_3DSTATE_WM(r->builder, vec->fs, num_samplers,
struct gen6_draw_session *session)
{
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
- if (DIRTY(FB) || session->batch_bo_changed) {
+ if (DIRTY(FB) || r->batch_bo_changed) {
const struct ilo_zs_surface *zs;
uint32_t clear_params;
}
void
-gen6_draw_prepare(const struct ilo_render *render,
+gen6_draw_prepare(struct ilo_render *render,
const struct ilo_state_vector *vec,
struct gen6_draw_session *session)
{
session->pipe_dirty = vec->dirty;
session->reduced_prim = u_reduced_prim(vec->draw->mode);
- session->hw_ctx_changed =
- (render->invalidate_flags & ILO_RENDER_INVALIDATE_HW);
-
- if (session->hw_ctx_changed) {
+ if (render->hw_ctx_changed) {
/* these should be enough to make everything uploaded */
- session->batch_bo_changed = true;
- session->state_bo_changed = true;
- session->kernel_bo_changed = true;
+ render->batch_bo_changed = true;
+ render->state_bo_changed = true;
+ render->instruction_bo_changed = true;
+
session->prim_changed = true;
session->primitive_restart_changed = true;
} else {
- /*
- * Any state that involves resources needs to be re-emitted when the
- * batch bo changed. This is because we do not pin the resources and
- * their offsets (or existence) may change between batch buffers.
- */
- session->batch_bo_changed =
- (render->invalidate_flags & ILO_RENDER_INVALIDATE_BATCH_BO);
-
- session->state_bo_changed =
- (render->invalidate_flags & ILO_RENDER_INVALIDATE_STATE_BO);
- session->kernel_bo_changed =
- (render->invalidate_flags & ILO_RENDER_INVALIDATE_KERNEL_BO);
session->prim_changed =
(render->state.reduced_prim != session->reduced_prim);
session->primitive_restart_changed =
struct gen6_draw_session *session)
{
/* force all states to be uploaded if the state bo changed */
- if (session->state_bo_changed)
+ if (render->state_bo_changed)
session->pipe_dirty = ILO_DIRTY_ALL;
else
session->pipe_dirty = vec->dirty;
session->emit_draw_states(render, vec, session);
/* force all commands to be uploaded if the HW context changed */
- if (session->hw_ctx_changed)
+ if (render->hw_ctx_changed)
session->pipe_dirty = ILO_DIRTY_ALL;
else
session->pipe_dirty = vec->dirty;
const struct ilo_state_vector *vec,
struct gen6_draw_session *session)
{
+ render->hw_ctx_changed = false;
+
+ render->batch_bo_changed = false;
+ render->state_bo_changed = false;
+ render->instruction_bo_changed = false;
+
render->state.reduced_prim = session->reduced_prim;
render->state.primitive_restart = vec->draw->primitive_restart;
}
struct gen6_draw_session *session)
{
/* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
- if (session->hw_ctx_changed) {
+ if (r->hw_ctx_changed) {
/*
* Push constant buffers are only allowed to take up at most the first
* 16KB of the URB. Split the space evenly for VS and FS.
/* see gen6_draw_vs() */
const bool emit_3dstate_constant_vs = session->pcb_state_vs_changed;
const bool emit_3dstate_vs = (DIRTY(VS) || DIRTY(SAMPLER_VS) ||
- session->kernel_bo_changed);
+ r->instruction_bo_changed);
/* emit depth stall before any of the VS commands */
if (emit_3dstate_binding_table || emit_3dstate_sampler_state ||
struct gen6_draw_session *session)
{
/* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
- if (session->hw_ctx_changed) {
+ if (r->hw_ctx_changed) {
gen7_3DSTATE_CONSTANT_HS(r->builder, 0, 0, 0);
gen7_3DSTATE_HS(r->builder, NULL, 0);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_HS */
- if (session->hw_ctx_changed)
+ if (r->hw_ctx_changed)
gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(r->builder, 0);
}
struct gen6_draw_session *session)
{
/* 3DSTATE_TE */
- if (session->hw_ctx_changed)
+ if (r->hw_ctx_changed)
gen7_3DSTATE_TE(r->builder);
}
struct gen6_draw_session *session)
{
/* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
- if (session->hw_ctx_changed) {
+ if (r->hw_ctx_changed) {
gen7_3DSTATE_CONSTANT_DS(r->builder, 0, 0, 0);
gen7_3DSTATE_DS(r->builder, NULL, 0);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_DS */
- if (session->hw_ctx_changed)
+ if (r->hw_ctx_changed)
gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(r->builder, 0);
}
struct gen6_draw_session *session)
{
/* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
- if (session->hw_ctx_changed) {
+ if (r->hw_ctx_changed) {
gen7_3DSTATE_CONSTANT_GS(r->builder, 0, 0, 0);
gen7_3DSTATE_GS(r->builder, NULL, 0);
}
so_info = ilo_shader_get_kernel_so_info(shader);
/* 3DSTATE_SO_BUFFER */
- if ((DIRTY(SO) || dirty_sh || session->batch_bo_changed) &&
+ if ((DIRTY(SO) || dirty_sh || r->batch_bo_changed) &&
vec->so.enabled) {
int i;
/* 3DSTATE_PS */
if (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND) ||
- session->kernel_bo_changed) {
+ r->instruction_bo_changed) {
const int num_samplers = vec->sampler[PIPE_SHADER_FRAGMENT].count;
const bool dual_blend = vec->blend->dual_blend;
if ((ilo_dev_gen(r->dev) == ILO_GEN(7) ||
ilo_dev_gen(r->dev) == ILO_GEN(7.5)) &&
- session->hw_ctx_changed)
+ r->hw_ctx_changed)
gen7_wa_pre_3dstate_ps_max_threads(r);
gen7_3DSTATE_PS(r->builder, vec->fs, num_samplers, dual_blend);
const bool emit_3dstate_ps =
(DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND));
const bool emit_3dstate_depth_buffer =
- (DIRTY(FB) || DIRTY(DSA) || session->state_bo_changed);
+ (DIRTY(FB) || DIRTY(DSA) || r->state_bo_changed);
if (emit_3dstate_ps ||
session->pcb_state_fs_changed ||
}
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
- if (DIRTY(FB) || session->batch_bo_changed) {
+ if (DIRTY(FB) || r->batch_bo_changed) {
const struct ilo_zs_surface *zs;
uint32_t clear_params;