rs6000: Rename DFP iterator and attr to DDTD and q

This is more in line with the other iterators we have, and a bit easier
to read and write.

	* config/rs6000/dfp.md (D64_D128): Rename to ...
	(DDTD): ... this, throughout.
	(dfp_suffix): Rename to ...
	(q): ... this, throughout.

From-SVN: r274218

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f9ebc668e621f8db67195a04953c5b473f20ce1f..f440b86f6b7a67e2fc2fea616d78bce70da4a716 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-08-08  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/dfp.md (D64_D128): Rename to ...
+       (DDTD): ... this, throughout.
+       (dfp_suffix): Rename to ...
+       (q): ... this, throughout.
+
 2019-08-08  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/dfp.md (D64_D128): Move earlier in the file.

diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 61ede5d2445b3a265fbc2cd027195fd2d9b87084..659b3c9a39be6cc0d10b6d703fb1a738962b57e0 100644 (file)
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -29,10 +29,9 @@
   ])
 
 ; Either of the two decimal modes.
-(define_mode_iterator D64_D128 [DD TD])
+(define_mode_iterator DDTD [DD TD])
 
-(define_mode_attr dfp_suffix [(DD "")
-                             (TD "q")])
+(define_mode_attr q [(DD "") (TD "q")])
 
 
 (define_insn "movsd_store"
@@ -157,43 +156,43 @@
    (set_attr "length" "8")])
 
 (define_insn "add<mode>3"
-  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-       (plus:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "%d")
-                      (match_operand:D64_D128 2 "gpc_reg_operand" "d")))]
+  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
+       (plus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
+                  (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
   "TARGET_DFP"
-  "dadd<dfp_suffix> %0,%1,%2"
+  "dadd<q> %0,%1,%2"
   [(set_attr "type" "dfp")])
 
 (define_insn "sub<mode>3"
-  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-       (minus:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "d")
-                       (match_operand:D64_D128 2 "gpc_reg_operand" "d")))]
+  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
+       (minus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")
+                   (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
   "TARGET_DFP"
-  "dsub<dfp_suffix> %0,%1,%2"
+  "dsub<q> %0,%1,%2"
   [(set_attr "type" "dfp")])
 
 (define_insn "mul<mode>3"
-  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-       (mult:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "%d")
-                      (match_operand:D64_D128 2 "gpc_reg_operand" "d")))]
+  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
+       (mult:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
+                  (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
   "TARGET_DFP"
-  "dmul<dfp_suffix> %0,%1,%2"
+  "dmul<q> %0,%1,%2"
   [(set_attr "type" "dfp")])
 
 (define_insn "div<mode>3"
-  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-       (div:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "d")
-                     (match_operand:D64_D128 2 "gpc_reg_operand" "d")))]
+  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
+       (div:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")
+                 (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
   "TARGET_DFP"
-  "ddiv<dfp_suffix> %0,%1,%2"
+  "ddiv<q> %0,%1,%2"
   [(set_attr "type" "dfp")])
 
 (define_insn "*cmp<mode>_internal1"
   [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
-       (compare:CCFP (match_operand:D64_D128 1 "gpc_reg_operand" "d")
-                     (match_operand:D64_D128 2 "gpc_reg_operand" "d")))]
+       (compare:CCFP (match_operand:DDTD 1 "gpc_reg_operand" "d")
+                     (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
   "TARGET_DFP"
-  "dcmpu<dfp_suffix> %0,%1,%2"
+  "dcmpu<q> %0,%1,%2"
   [(set_attr "type" "dfp")])
 
 (define_insn "floatdidd2"
@@ -214,10 +213,10 @@
 ;; This is the first stage of converting it to an integer type.
 
 (define_insn "ftrunc<mode>2"
-  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-       (fix:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "d")))]
+  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
+       (fix:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
   "TARGET_DFP"
-  "drintn<dfp_suffix>. 0,%0,%1,1"
+  "drintn<q>. 0,%0,%1,1"
   [(set_attr "type" "dfp")])
 
 ;; Convert a decimal64/128 whose value is an integer to an actual integer.
@@ -225,9 +224,9 @@
 
 (define_insn "fix<mode>di2"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
-       (fix:DI (match_operand:D64_D128 1 "gpc_reg_operand" "d")))]
+       (fix:DI (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
   "TARGET_DFP"
-  "dctfix<dfp_suffix> %0,%1"
+  "dctfix<q> %0,%1"
   [(set_attr "type" "dfp")])
 \f
 ;; Decimal builtin support
@@ -244,64 +243,61 @@
 (define_code_iterator DFP_TEST [eq lt gt unordered])
 
 (define_insn "dfp_ddedpd_<mode>"
-  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-       (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i")
-                         (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
-                        UNSPEC_DDEDPD))]
+  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
+       (unspec:DDTD [(match_operand:QI 1 "const_0_to_3_operand" "i")
+                     (match_operand:DDTD 2 "gpc_reg_operand" "d")]
+                    UNSPEC_DDEDPD))]
   "TARGET_DFP"
-  "ddedpd<dfp_suffix> %1,%0,%2"
+  "ddedpd<q> %1,%0,%2"
   [(set_attr "type" "dfp")])
 
 (define_insn "dfp_denbcd_<mode>"
-  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-       (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i")
-                         (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
-                        UNSPEC_DENBCD))]
+  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
+       (unspec:DDTD [(match_operand:QI 1 "const_0_to_1_operand" "i")
+                     (match_operand:DDTD 2 "gpc_reg_operand" "d")]
+                    UNSPEC_DENBCD))]
   "TARGET_DFP"
-  "denbcd<dfp_suffix> %1,%0,%2"
+  "denbcd<q> %1,%0,%2"
   [(set_attr "type" "dfp")])
 
 (define_insn "dfp_dxex_<mode>"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
-       (unspec:DI [(match_operand:D64_D128 1 "gpc_reg_operand" "d")]
+       (unspec:DI [(match_operand:DDTD 1 "gpc_reg_operand" "d")]
                   UNSPEC_DXEX))]
   "TARGET_DFP"
-  "dxex<dfp_suffix> %0,%1"
+  "dxex<q> %0,%1"
   [(set_attr "type" "dfp")])
 
 (define_insn "dfp_diex_<mode>"
-  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-       (unspec:D64_D128 [(match_operand:DI 1 "gpc_reg_operand" "d")
-                         (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
-                        UNSPEC_DXEX))]
+  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
+       (unspec:DDTD [(match_operand:DI 1 "gpc_reg_operand" "d")
+                     (match_operand:DDTD 2 "gpc_reg_operand" "d")]
+                    UNSPEC_DXEX))]
   "TARGET_DFP"
-  "diex<dfp_suffix> %0,%1,%2"
+  "diex<q> %0,%1,%2"
   [(set_attr "type" "dfp")])
 
 (define_expand "dfptstsfi_<code>_<mode>"
   [(set (match_dup 3)
-       (compare:CCFP
-         (unspec:D64_D128
-         [(match_operand:SI 1 "const_int_operand")
-          (match_operand:D64_D128 2 "gpc_reg_operand")]
-         UNSPEC_DTSTSFI)
-        (match_dup 4)))
+       (compare:CCFP (unspec:DDTD [(match_operand:SI 1 "const_int_operand")
+                                   (match_operand:DDTD 2 "gpc_reg_operand")]
+                                  UNSPEC_DTSTSFI)
+                     (const_int 0)))
    (set (match_operand:SI 0 "register_operand")
-       (DFP_TEST:SI (match_dup 3)
+       (DFP_TEST:SI (match_dup 3)
                     (const_int 0)))
   ]
   "TARGET_P9_MISC"
 {
   operands[3] = gen_reg_rtx (CCFPmode);
-  operands[4] = const0_rtx;
 })
 
 (define_insn "*dfp_sgnfcnc_<mode>"
   [(set (match_operand:CCFP 0 "" "=y")
-        (compare:CCFP
-        (unspec:D64_D128 [(match_operand:SI 1 "const_int_operand" "n")
-                          (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
-          UNSPEC_DTSTSFI)
+       (compare:CCFP
+        (unspec:DDTD [(match_operand:SI 1 "const_int_operand" "n")
+                      (match_operand:DDTD 2 "gpc_reg_operand" "d")]
+                     UNSPEC_DTSTSFI)
         (match_operand:SI 3 "zero_constant" "j")))]
   "TARGET_P9_MISC"
 {
@@ -310,24 +306,24 @@
      immediate operand values greater than 63.  */
   if (!(IN_RANGE (INTVAL (operands[1]), 0, 63)))
     operands[1] = GEN_INT (63);
-  return "dtstsfi<dfp_suffix> %0,%1,%2";
+  return "dtstsfi<q> %0,%1,%2";
 }
   [(set_attr "type" "fp")])
 
 (define_insn "dfp_dscli_<mode>"
-  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-       (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
-                         (match_operand:QI 2 "immediate_operand" "i")]
-                        UNSPEC_DSCLI))]
+  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
+       (unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
+                     (match_operand:QI 2 "immediate_operand" "i")]
+                    UNSPEC_DSCLI))]
   "TARGET_DFP"
-  "dscli<dfp_suffix> %0,%1,%2"
+  "dscli<q> %0,%1,%2"
   [(set_attr "type" "dfp")])
 
 (define_insn "dfp_dscri_<mode>"
-  [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
-       (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
-                         (match_operand:QI 2 "immediate_operand" "i")]
-                        UNSPEC_DSCRI))]
+  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
+       (unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
+                     (match_operand:QI 2 "immediate_operand" "i")]
+                    UNSPEC_DSCRI))]
   "TARGET_DFP"
-  "dscri<dfp_suffix> %0,%1,%2"
+  "dscri<q> %0,%1,%2"
   [(set_attr "type" "dfp")])