radv: Add support for IMG_DATA_FORMAT_32_32_32.

Basic sampling support for linear tiling.

No CTS regressions, but it seems the blitting coverage is not very
extensive.

https://bugs.freedesktop.org/show_bug.cgi?id=106331
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 12240c93d6b6b7bc5a5adc79708e702d80a581cc..9e742dc8a4501f7ebf20cb099c6c23e96716f989 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1320,6 +1320,10 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
                        assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
                        AddrSurfInfoIn.format = ADDR_FMT_32_32;
                        break;
+               case 12:
+                       assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
+                       AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
+                       break;
                case 16:
                        assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
                        AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;

diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 1bafe09e77f2f3cc09274387ade6b169cdcfa306..f8438f43b85e8fc2cddff9cc247905fcd0137726 100644 (file)
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -321,10 +321,8 @@ uint32_t radv_translate_tex_dataformat(VkFormat format,
                        return V_008F14_IMG_DATA_FORMAT_32;
                case 2:
                        return V_008F14_IMG_DATA_FORMAT_32_32;
-#if 0 /* Not supported for render targets */
                case 3:
                        return V_008F14_IMG_DATA_FORMAT_32_32_32;
-#endif
                case 4:
                        return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
                }
@@ -638,13 +636,17 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical
                                tiled |= VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT;
                        }
                }
-               if (tiled && util_is_power_of_two_or_zero(vk_format_get_blocksize(format)) && !scaled) {
+               if (tiled && !scaled) {
                        tiled |= VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
                                 VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR;
                }
+
+               /* Tiled formatting does not support NPOT pixel sizes */
+               if (!util_is_power_of_two_or_zero(vk_format_get_blocksize(format)))
+                       tiled = 0;
        }
 
-       if (linear && util_is_power_of_two_or_zero(vk_format_get_blocksize(format)) && !scaled) {
+       if (linear && !scaled) {
                linear |= VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
                          VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR;
        }

diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c
index 2055289a9bb1e310b6743e97a68acd8f1dd9d8ad..1f18886d2c5f56ec0923938a13e70e02bf125a26 100644 (file)
--- a/src/amd/vulkan/radv_meta_copy.c
+++ b/src/amd/vulkan/radv_meta_copy.c
@@ -72,6 +72,7 @@ vk_format_for_size(int bs)
        case 2: return VK_FORMAT_R8G8_UINT;
        case 4: return VK_FORMAT_R8G8B8A8_UINT;
        case 8: return VK_FORMAT_R16G16B16A16_UINT;
+       case 12: return VK_FORMAT_R32G32B32_UINT;
        case 16: return VK_FORMAT_R32G32B32A32_UINT;
        default:
                unreachable("Invalid format block size");