radeonsi: Fix hardware state for dual source blending

Set up CB_SHADER_MASK register according to pixel shader exports, and enable
some minimal state for colour buffer 1 in case dual source blending is used.

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index 484f7ecfcdb0bbddd0a67d0f3f62e57ac4d29fba..3e023f8600d1ecff49250567561b59491ef6570f 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -461,6 +461,8 @@ static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
                        else
                                si_shader_ctx->shader->spi_shader_col_format |=
                                        V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
+
+                       si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
                }
        }
 
@@ -806,6 +808,7 @@ static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
 
                si_shader_ctx->shader->spi_shader_col_format |=
                        V_028714_SPI_SHADER_32_ABGR;
+               si_shader_ctx->shader->cb_shader_mask |= S_02823C_OUTPUT0_ENABLE(0xf);
        }
 
        /* Specify whether the EXEC mask represents the valid mask */
@@ -830,6 +833,8 @@ static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
 
                        si_shader_ctx->shader->spi_shader_col_format |=
                                si_shader_ctx->shader->spi_shader_col_format << 4;
+                       si_shader_ctx->shader->cb_shader_mask |=
+                               si_shader_ctx->shader->cb_shader_mask << 4;
                }
 
                last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.h b/src/gallium/drivers/radeonsi/radeonsi_shader.h
index 01b8b5d3b734c5eef8c6ced19ff948e6c621d010..33e81c7d6d0d3027b5208467d2d37e425aa3b4a3 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h
@@ -140,6 +140,7 @@ struct si_pipe_shader {
        unsigned                        num_vgprs;
        unsigned                        spi_ps_input_ena;
        unsigned                        spi_shader_col_format;
+       unsigned                        cb_shader_mask;
        unsigned                        sprite_coord_enable;
        unsigned                        so_strides[4];
        union si_shader_key             key;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index dec535ca597218d86dca09be6407427b61b50d27..e7dc792b93cc8bdbfd06c1a52f2b583f7b0081ab 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1728,6 +1728,12 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
        si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
        si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
 
+       /* set CB_COLOR1_INFO for possible dual-src blending */
+       if (state->nr_cbufs == 1) {
+               assert(cb == 0);
+               si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
+       }
+
        /* Determine pixel shader export format */
        max_comp_size = si_colorformat_max_comp_size(format);
        if (ntype == V_028C70_NUMBER_SRGB ||
@@ -1735,6 +1741,9 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
             max_comp_size <= 10) ||
            (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
                rctx->export_16bpc |= 1 << cb;
+               /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
+               if (state->nr_cbufs == 1)
+                       rctx->export_16bpc |= 1 << 1;
        }
 }
 
@@ -1811,7 +1820,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
 {
        struct r600_context *rctx = (struct r600_context *)ctx;
        struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
-       uint32_t shader_mask, tl, br;
+       uint32_t tl, br;
        int tl_x, tl_y, br_x, br_y;
 
        if (pm4 == NULL)
@@ -1832,10 +1841,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
        assert(!(rctx->export_16bpc & ~0xff));
        si_db(rctx, pm4, state);
 
-       shader_mask = 0;
-       for (int i = 0; i < state->nr_cbufs; i++) {
-               shader_mask |= 0xf << (i * 4);
-       }
        tl_x = 0;
        tl_y = 0;
        br_x = state->width;
@@ -1854,7 +1859,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
        si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
        si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
        si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
-       si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
        si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
 
        si_pm4_set_state(rctx, framebuffer, pm4);

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index ae571a4fb54ce3fd2e465769d640828150745116..09c741fa3f13b8bb5cafe5813a61ebe5b94bc3c1 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -213,6 +213,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
        si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
        si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
                       shader->spi_shader_col_format);
+       si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
 
        va = r600_resource_va(ctx->screen, (void *)shader->bo);
        si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);