LX -> LP

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 34134d02af838bf856125fe64dda5a1845642f0d..fe80c998d9a3f28b515643ca444dfc45c99e5a36 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -3,7 +3,7 @@
 // `define SB_DFF_REG reg Q
 
 `define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
-`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
 `define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
 
 // SiliconBlue IO Cells