add "attn" 16-bit instruction

diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn
index f9f019763cc5359c712c6802c5ead0b5112f0d20..e3b1d23145453f82cc795026efc64874e6c04584 100644 (file)
--- a/openpower/sv/16_bit_compressed.mdwn
+++ b/openpower/sv/16_bit_compressed.mdwn
@@ -244,7 +244,7 @@ Further Notes:
   - this only works if RT takes part of opcode
   - mv is also possible by specifying an immediate of zero
 
-### Illegal and nop
+### Illegal, nop and attn
 
 Note that illeg is all zeros, including in the 16-bit mode.
 Given that C is allocated to OpenPOWER ISA Major opcodes EXT000 and
@@ -260,6 +260,7 @@ is "nop"
 16 bit mode only:
 
     | 1 | 0   000 | | 000.0  | 0  00 | 0   00 | 0 | nop
+    | 1 | 1   000 | | 000.0  | 0  00 | 0   00 | 0 | attn
     | 1 | nonzero | | 000.0  | 0  00 | 0   00 | 0 | TBD
 
 Notes: