add section on different RV standards

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index f038e9903015556f777badc6d2e1884581f4b4d7..1522233ac72661ad3a7b1a65eb0b4d6f684cb851 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -1068,6 +1068,10 @@ CSR Register table is either 4 16-bit entries or (if the U-Mode is
 zero) only 2 16-bit entries (M-Mode CSR table only).  Likewise for
 the Predication CSR tables.
 
+RV32E is the most likely candidate for simply detecting that registers
+are marked as "vectorised", and generating an appropriate exception
+for the VL loop to be implemented in software.
+
 ## RV128
 
 RV128 has not been especially considered, here, however it has some