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diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 3bfc3e8c1525abe22180016362971cb8bb5bdb21..2e136f8adb7656c025ebc51f66b65d006792fe5d 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -36,7 +36,7 @@ is as if the
 When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed.  See appendix for details.
 * **Pack/Unpack** mode, only available when SUBVL is vec2/3/4, performs
 basic structure packing on sub-elements. Bits 4-5 (normally elwidth) are
-taken up as Pack/Unpack bits.
+taken up as Pack/Unpack bits. Saturation may be simultaneously enabled.
 
 Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations.  ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result.  normal, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL.