| Encoding | Available bits | Scalar | Vectoriseable | SVP64Single |
|----------|----------------|--------|---------------|--------------|
|EXT000-063| 32 | yes | yes |yes |
-|EXT100-163| 64 (?) | yes | no |no |
-|RESERVED2 | 57 | N/A |not applicable |not applicable|
+|EXT100-163| 64 | yes | no |no |
+|R3SERVED2 | 57 | N/A |not applicable |not applicable|
|EXT232-263| 32 | yes | yes |yes |
|RESERVED1 | 32 | N/A | no |no |
-Prefixed-Prefixed (96-bit) instructions are prohibited. RESERVED2 presently
-remains unallocated as of yet and therefore its potential is not yet defined
-(Not Applicable). RESERVED1 is also unallocated at present, but it is
-known in advance that the area is UnVectoriseable and also cannot be
-Prefixed with SVP64Single.
+Notes:
+
+* Prefixed-Prefixed (96-bit) instructions are prohibited. EXT1xx is
+ thus inherently UnVectoriseable as the EXT1xx prefix is 32-bit
+ on top of an SVP64 prefix which is 32-bit on top of a Defined Word
+ and the complexity at the Decoder becomes too great for High
+ Performance Multi-Issue systems.
+* RESERVED2 presently remains unallocated as of yet and therefore its
+ potential is not yet defined (Not Applicable).
+* RESERVED1 is also unallocated at present, but it is known in advance
+ that the area is UnVectoriseable and also cannot be Prefixed with
+ SVP64Single.
+* Considerable care is needed both on Architectural Resource Allocation
+ as well as instruction design itself. Once an instruction is allocated
+ in an UnVectoriseable area it can never be Vectorised without providing
+ an entirely new Encoding.
# Remapped Encoding (`RM[0:23]`)