abc9_ops: -prep_dff_map to warn if no specify cells

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index cf3bd689e1bbcfae9b95785961101fce4b76046f..c640d06f82ab1e5bc7d62435605b98bf38c1cb68 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -206,13 +206,18 @@ void prep_dff_map(RTLIL::Design *design)
                        D = w;
                }
 
-               // Rewrite $specify cells that end with $_DFF_[NP]_.Q
-               //   to $_DFF_[NP]_.D since it will be moved into
-               //   the submodule
-               for (auto cell : specify_cells) {
-                       auto DST = cell->getPort(ID::DST);
-                       DST.replace(Q, D);
-                       cell->setPort(ID::DST, DST);
+               if (GetSize(specify_cells) == 0) {
+                       log_warning("Module '%s' marked (* abc9_flop *) contains no specify timing information.\n", log_id(module));
+               }
+               else {
+                       // Rewrite $specify cells that end with $_DFF_[NP]_.Q
+                       //   to $_DFF_[NP]_.D since it will be moved into
+                       //   the submodule
+                       for (auto cell : specify_cells) {
+                               auto DST = cell->getPort(ID::DST);
+                               DST.replace(Q, D);
+                               cell->setPort(ID::DST, DST);
+                       }
                }
 continue_outer_loop: ;
        }