use RS in bmask.py not RT

diff --git a/openpower/simple_v_spec.tex b/openpower/simple_v_spec.tex
index 01a04d196e0817c4118ec847949ea6cbf250ed82..22d042c98936af1a8994931ad84ac291c7da3cbd 100644 (file)
--- a/openpower/simple_v_spec.tex
+++ b/openpower/simple_v_spec.tex
@@ -308,7 +308,7 @@ to benefit.  It also makes proposal much easier, as there is no
 inter-dependence.
 
 It is however important to note that the rationale for these instructions
-comes from a more general-purpose moderen computing paradigm that is
+comes from a more general-purpose modern computing paradigm that is
 outside of IBM's much more focussed and specialist traditional customer
 base. We deeply respect IBM's curator role of the Power ISA of the past 25
 years as much as we appreciate their courage in transferring that role

diff --git a/openpower/sv/bmask.py b/openpower/sv/bmask.py
index f64708bce54c8baffd11b631f38af31403b58237..391b279ce7cf9511d0d3618e41193f0128e52b73 100644 (file)
--- a/openpower/sv/bmask.py
+++ b/openpower/sv/bmask.py
@@ -11,14 +11,15 @@ def bmask(bm, RA, RB=None, zero=False, XLEN=64):
     a1 = a1 & mask
     a2 = a2 & mask
     mode3 = (bm >> 3) & 0b11
-    if mode3 == 0: RT = a1 | a2
-    if mode3 == 1: RT = a1 & a2
-    if mode3 == 2: RT = a1 ^ a2
-    if mode3 == 3: RT = 0 # UNDEFINED
-    RT &= mask
+    if mode3 == 0: RS = a1 | a2
+    if mode3 == 1: RS = a1 & a2
+    if mode3 == 2: RS = a1 ^ a2
+    if mode3 == 3: RS = 0 # RESERVED
+    RS &= mask
     if not zero:
-        RT |= RA & ~mask
-    return RT
+        # put back masked-out bits of RA
+        RS |= RA & ~mask
+    return RS
 
 SBF = 0b01010 # set before first
 SOF = 0b01001 # set only first