add option to run without a disassembly listing to ISACaller

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index effaa1234ede7f4c8c2f005e043c43a8063c0c59..4ea2061a174b37964f8b7ec81062e6a4240b2ec7 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -851,10 +851,16 @@ class ISACaller:
         """
         # get the disassembly code for this instruction
         if self.is_svp64_mode:
-            code = self.disassembly[self._pc+4]
+            if not self.disassembly:
+                code = yield from self.get_assembly_name()
+            else:
+                code = self.disassembly[self._pc+4]
             print("    svp64 sim-execute", hex(self._pc), code)
         else:
-            code = self.disassembly[self._pc]
+            if not self.disassembly:
+                code = yield from self.get_assembly_name()
+            else:
+                code = self.disassembly[self._pc]
             print("sim-execute", hex(self._pc), code)
         opname = code.split(' ')[0]
         try:

diff --git a/src/openpower/decoder/isa/pypowersim.py b/src/openpower/decoder/isa/pypowersim.py
index 9bee15a585ca1962457abeab473c77ee83bfc658..ca0a490071573572efb257906178d57bb4702f0a 100644 (file)
--- a/src/openpower/decoder/isa/pypowersim.py
+++ b/src/openpower/decoder/isa/pypowersim.py
@@ -66,8 +66,12 @@ def run_tst(args, generator, initial_regs,
     pdecode = create_pdecode(include_fp=initial_fprs is not None)
 
     gen = list(generator.generate_instructions())
+    print ("instructions gen", gen)
     insncode = generator.assembly.splitlines()
-    instructions = list(zip(gen, insncode))
+    if insncode:
+        instructions = list(zip(gen, insncode))
+    else:
+        instructions = gen
 
     print ("instructions", instructions)
 
@@ -96,10 +100,14 @@ def run_tst(args, generator, initial_regs,
                 break
             yield Settle()
 
-            ins, code = instructions[index]
-            print("    0x{:X}".format(ins & 0xffffffff))
-            opname = code.split(' ')[0]
-            print(code, opname)
+            ins = instructions[index]
+            if isinstance(ins, list):
+                ins, code = ins
+                print("    0x{:X}".format(ins & 0xffffffff))
+                opname = code.split(' ')[0]
+                print(code, opname)
+            else:
+                print("    0x{:X}".format(ins & 0xffffffff))
 
             # ask the decoder to decode this binary data (endian'd)
             yield from simulator.execute_one()

diff --git a/src/openpower/simulator/program.py b/src/openpower/simulator/program.py
index f289abe5e351f4100ddfd5bcd3da97b743710f2b..96747e1b56d618860ad5948700e0b2f1112b7a91 100644 (file)
--- a/src/openpower/simulator/program.py
+++ b/src/openpower/simulator/program.py
@@ -37,6 +37,7 @@ class Program:
             self.binfile = BytesIO(instructions)
             self.binfile.name = "assembly"
             self.assembly = ''  # noo disassemble number fiiive
+            print("binary", self.binfile)
         elif isinstance(instructions, str):  # filename
             # read instructions into a BytesIO to avoid "too many open files"
             with open(instructions, "rb") as f: