i386.h (TUNEMASK): Remove define.

        * config/i386/i386.h (TUNEMASK): Remove define.
        (ARCHMASK): Remove define.
        (TARGET_*): Use ix86_tune_mask variable instead of TUNEMASK.
         Use ix86_arch_mask variable instead of ARCHMASK.
        * config/i386/i386.c (override_options): Ditto.
        (standard_80387_constant_p): Ditto.

From-SVN: r122491

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0976767deed6e1c5f06fcf78d2e4ff267e85679c..39f849a3522e9353786a0c04f30115300d2ffe4a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2007-03-02  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.h (TUNEMASK): Remove define.
+       (ARCHMASK): Remove define.
+       (TARGET_*): Use ix86_tune_mask variable instead of TUNEMASK.
+        Use ix86_arch_mask variable instead of ARCHMASK.
+       * config/i386/i386.c (override_options): Ditto.
+       (standard_80387_constant_p): Ditto.
+
 2007-03-03  Ian Lance Taylor  <iant@google.com>
 
        Used signed infinities in VRP.

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index bdf76d3196e213ec6c931830bfd0fd182d7a2e49..cc0b2754d5a6023d206c43dd9da0cdd7c2ebc642 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2284,7 +2284,7 @@ override_options (void)
 
   /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
      since the insns won't need emulation.  */
-  if (x86_arch_always_fancy_math_387 & ARCHMASK)
+  if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
     target_flags &= ~MASK_NO_FANCY_MATH_387;
 
   /* Likewise, if the target doesn't have a 387, or we've specified
@@ -2405,7 +2405,7 @@ override_options (void)
   if (!TARGET_80387)
     target_flags &= ~MASK_FLOAT_RETURNS;
 
-  if ((x86_accumulate_outgoing_args & TUNEMASK)
+  if ((x86_accumulate_outgoing_args & ix86_tune_mask)
       && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
       && !optimize_size)
     target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
@@ -4999,7 +4999,7 @@ standard_80387_constant_p (rtx x)
   /* For XFmode constants, try to find a special 80387 instruction when
      optimizing for size or on those CPUs that benefit from them.  */
   if (GET_MODE (x) == XFmode
-      && (optimize_size || x86_ext_80387_constants & TUNEMASK))
+      && (optimize_size || x86_ext_80387_constants & ix86_tune_mask))
     {
       int i;
 

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index e319b770f94c68170ceb827a5d8732e17375a7c2..f77fc766462fff6b349110ef8282b8ee278e2175 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -207,65 +207,65 @@ extern const int x86_bswap;
 extern const int x86_partial_flag_reg_stall;
 extern int x86_prefetch_sse, x86_cmpxchg16b;
 
-#define TUNEMASK ix86_tune_mask
-#define ARCHMASK ix86_arch_mask
-
-#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
-#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
-#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
-#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
-#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
+#define TARGET_USE_LEAVE (x86_use_leave & ix86_tune_mask)
+#define TARGET_PUSH_MEMORY (x86_push_memory & ix86_tune_mask)
+#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & ix86_tune_mask)
+#define TARGET_USE_BIT_TEST (x86_use_bit_test & ix86_tune_mask)
+#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & ix86_tune_mask)
 /* For sane SSE instruction set generation we need fcomi instruction.  It is
    safe to enable all CMOVE instructions.  */
-#define TARGET_CMOVE ((x86_cmove & ARCHMASK) || TARGET_SSE)
+#define TARGET_CMOVE ((x86_cmove & ix86_arch_mask) || TARGET_SSE)
 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
-#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
-#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
-#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
-#define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
-#define TARGET_MOVX (x86_movx & TUNEMASK)
-#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
-#define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK)
-#define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK)
-#define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK)
-#define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
-#define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
-#define TARGET_USE_XCHGB (x86_use_xchgb & TUNEMASK)
-#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
-#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
-#define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
-#define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
-#define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
-#define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
-#define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
-#define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
-#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
-#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
-#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
-#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
-#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
-#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
-#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
-#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
-#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
-                                     (x86_sse_partial_reg_dependency & TUNEMASK)
-#define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
-                                     (x86_sse_unaligned_move_optimal & TUNEMASK)
-#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
-#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
-#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
-#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
-#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
-#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
+#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & ix86_tune_mask)
+#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & ix86_tune_mask)
+#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & ix86_tune_mask)
+#define TARGET_USE_SAHF ((x86_use_sahf & ix86_tune_mask) && !TARGET_64BIT)
+#define TARGET_MOVX (x86_movx & ix86_tune_mask)
+#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & ix86_tune_mask)
+#define TARGET_PARTIAL_FLAG_REG_STALL          \
+  (x86_partial_flag_reg_stall & ix86_tune_mask)
+#define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & ix86_tune_mask)
+#define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & ix86_tune_mask)
+#define TARGET_USE_MOV0 (x86_use_mov0 & ix86_tune_mask)
+#define TARGET_USE_CLTD (x86_use_cltd & ix86_tune_mask)
+#define TARGET_USE_XCHGB (x86_use_xchgb & ix86_tune_mask)
+#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & ix86_tune_mask)
+#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & ix86_tune_mask)
+#define TARGET_READ_MODIFY (x86_read_modify & ix86_tune_mask)
+#define TARGET_PROMOTE_QImode (x86_promote_QImode & ix86_tune_mask)
+#define TARGET_FAST_PREFIX (x86_fast_prefix & ix86_tune_mask)
+#define TARGET_SINGLE_STRINGOP (x86_single_stringop & ix86_tune_mask)
+#define TARGET_QIMODE_MATH (x86_qimode_math & ix86_tune_mask)
+#define TARGET_HIMODE_MATH (x86_himode_math & ix86_tune_mask)
+#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & ix86_tune_mask)
+#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & ix86_tune_mask)
+#define TARGET_ADD_ESP_4 (x86_add_esp_4 & ix86_tune_mask)
+#define TARGET_ADD_ESP_8 (x86_add_esp_8 & ix86_tune_mask)
+#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & ix86_tune_mask)
+#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & ix86_tune_mask)
+#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & ix86_tune_mask)
+#define TARGET_PARTIAL_REG_DEPENDENCY          \
+  (x86_partial_reg_dependency & ix86_tune_mask)
+#define TARGET_SSE_PARTIAL_REG_DEPENDENCY              \
+  (x86_sse_partial_reg_dependency & ix86_tune_mask)
+#define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL              \
+  (x86_sse_unaligned_move_optimal & ix86_tune_mask)
+#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & ix86_tune_mask)
+#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & ix86_tune_mask)
+#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & ix86_tune_mask)
+#define TARGET_MEMORY_MISMATCH_STALL           \
+  (x86_memory_mismatch_stall & ix86_tune_mask)
+#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & ix86_tune_mask)
+#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & ix86_tune_mask)
 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
-#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
-#define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
-#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
-#define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
-#define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
-#define TARGET_USE_BT (x86_use_bt & TUNEMASK)
-#define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK)
-#define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK)
+#define TARGET_SHIFT1 (x86_shift1 & ix86_tune_mask)
+#define TARGET_USE_FFREEP (x86_use_ffreep & ix86_tune_mask)
+#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & ix86_tune_mask)
+#define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & ix86_tune_mask)
+#define TARGET_SCHEDULE (x86_schedule & ix86_tune_mask)
+#define TARGET_USE_BT (x86_use_bt & ix86_tune_mask)
+#define TARGET_USE_INCDEC (x86_use_incdec & ix86_tune_mask)
+#define TARGET_PAD_RETURNS (x86_pad_returns & ix86_tune_mask)
 
 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
 
@@ -278,11 +278,11 @@ extern int x86_prefetch_sse, x86_cmpxchg16b;
 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
 
-#define TARGET_CMPXCHG (x86_cmpxchg & ARCHMASK)
-#define TARGET_CMPXCHG8B (x86_cmpxchg8b & ARCHMASK)
+#define TARGET_CMPXCHG (x86_cmpxchg & ix86_arch_mask)
+#define TARGET_CMPXCHG8B (x86_cmpxchg8b & ix86_arch_mask)
 #define TARGET_CMPXCHG16B (x86_cmpxchg16b)
-#define TARGET_XADD (x86_xadd & ARCHMASK)
-#define TARGET_BSWAP (x86_bswap & ARCHMASK)
+#define TARGET_XADD (x86_xadd & ix86_arch_mask)
+#define TARGET_BSWAP (x86_bswap & ix86_arch_mask)
 
 #ifndef TARGET_64BIT_DEFAULT
 #define TARGET_64BIT_DEFAULT 0