gen7 blorp depth: calculate base surface width/height

This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 9ce1a75839911065bc58d2b3f562d05e1ab8c7aa..920790a2b7903b76cf8e1067f3388dbd570abfd5 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -663,6 +663,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
    uint32_t draw_y = params->depth.y_offset;
    uint32_t tile_mask_x, tile_mask_y;
    uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+   uint32_t surfwidth, surfheight;
    uint32_t surftype;
    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
    unsigned int min_array_element;
@@ -698,6 +699,18 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    lod = params->depth.level - params->depth.mt->first_level;
 
+   if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
+      /* HIZ ops for lod 0 may set the width & height a little
+       * larger to allow the fast depth clear to fit the hardware
+       * alignment requirements. (8x4)
+       */
+      surfwidth = params->depth.width;
+      surfheight = params->depth.height;
+   } else {
+      surfwidth = params->depth.mt->physical_width0;
+      surfheight = params->depth.mt->physical_height0;
+   }
+
    /* 3DSTATE_DEPTH_BUFFER */
    {
       uint32_t tile_x = draw_x & tile_mask_x;