Fixed bug in freduce command
authorClifford Wolf <clifford@clifford.at>
Fri, 7 Mar 2014 17:44:23 +0000 (18:44 +0100)
committerClifford Wolf <clifford@clifford.at>
Fri, 7 Mar 2014 17:44:23 +0000 (18:44 +0100)
passes/sat/freduce.cc

index eb94cad280a7447e1811391bec4dd727d2329780..d4b7b5c10f9c7548afa0598f8fdd5b4cbb310feb 100644 (file)
@@ -560,6 +560,31 @@ struct FreduceWorker
        {
        }
 
+       bool find_bit_in_cone(std::set<RTLIL::Cell*> &celldone, RTLIL::SigBit needle, RTLIL::SigBit haystack)
+       {
+               if (needle == haystack)
+                       return true;
+               if (haystack.wire == NULL || needle.wire == NULL || drivers.count(haystack) == 0)
+                       return false;
+
+               std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(haystack);
+
+               if (celldone.count(drv.first))
+                       return false;
+               celldone.insert(drv.first);
+
+               for (auto &bit : drv.second)
+                       if (find_bit_in_cone(celldone, needle, bit))
+                               return true;
+               return false;
+       }
+
+       bool find_bit_in_cone(RTLIL::SigBit needle, RTLIL::SigBit haystack)
+       {
+               std::set<RTLIL::Cell*> celldone;
+               return find_bit_in_cone(celldone, needle, haystack);
+       }
+
        void dump()
        {
                std::string filename = stringf("%s_%s_%05d.il", dump_prefix.c_str(), RTLIL::id2cstr(module->name), reduce_counter);
@@ -674,6 +699,11 @@ struct FreduceWorker
                                        continue;
                                }
 
+                               if (find_bit_in_cone(grp[i].bit, grp.front().bit)) {
+                                       log("      Skipping dependency of master: %s\n", log_signal(grp[i].bit));
+                                       continue;
+                               }
+
                                log("      Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));
 
                                RTLIL::Cell *drv = drivers.at(grp[i].bit).first;