2008-12-15 Joel Sherrill <joel.sherrill@oarcorp.com>

	* ppc-instructions, ppc-spr-table: Add ability
	to read tbrl and tbru special registers.

diff --git a/sim/ppc/ChangeLog b/sim/ppc/ChangeLog
index 17f50cfd309101240e7ec414c9fc4ada4f1f3808..6e0febfa047c243002966a53afd3b8b018ed3163 100644 (file)
--- a/sim/ppc/ChangeLog
+++ b/sim/ppc/ChangeLog
@@ -1,3 +1,8 @@
+2008-12-15 Joel Sherrill <joel.sherrill@oarcorp.com>
+
+       * ppc-instructions, ppc-spr-table: Add ability
+       to read tbrl and tbru special registers.
+
 2008-11-18  Joel Sherrill <joel.sherrill@oarcorp.com>
 
        * configure: Regenerated.

diff --git a/sim/ppc/ppc-instructions b/sim/ppc/ppc-instructions
index 5f3e13319f63cfb0e2d2a840154d55d34896ff20..66c26fc949c3e3ebe7b8a6b6ac048a57388379f0 100644 (file)
--- a/sim/ppc/ppc-instructions
+++ b/sim/ppc/ppc-instructions
@@ -3402,6 +3402,14 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
            case spr_dec:
              *rT = cpu_get_decrementer(processor);
              break;
+               case spr_tbrl:
+                 if (is_64bit_implementation) *rT = TB;
+                 else                         *rT = EXTRACTED64(TB, 32, 63);
+               break;
+               case spr_tbru:
+                 if (is_64bit_implementation) *rT = EXTRACTED64(TB, 0, 31);
+                 else                         *rT = EXTRACTED64(TB, 0, 31);
+               break;
            case spr_tbu:
            case spr_tbl:
              /* NOTE - these SPR's are not readable. Use mftb[ul] */

diff --git a/sim/ppc/ppc-spr-table b/sim/ppc/ppc-spr-table
index 221ccbeacf09eda8725599b3a3979b48a04698ce..e224df97f4070452a0e308bd8f1f069f76644718 100644 (file)
--- a/sim/ppc/ppc-spr-table
+++ b/sim/ppc/ppc-spr-table
@@ -32,6 +32,8 @@ SDR1:25:0:0
 SRR0:26:0:0
 SRR1:27:0:0
 VRSAVE:256:0:0
+TBRL:268:0:0
+TBRU:269:0:0
 SPRG0:272:0:0
 SPRG1:273:0:0
 SPRG2:274:0:0