(no commit message)

diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn
index b86fd00fa0a5d213c69a2c18628e929beb2c60e8..b840540aca4f2e49f01eec15d330cc7e1799ae62 100644 (file)
--- a/3d_gpu/architecture/dynamic_simd.mdwn
+++ b/3d_gpu/architecture/dynamic_simd.mdwn
@@ -175,6 +175,7 @@ basic HDL is literally an order of magnitude larger:
 To save hugely on gate count the normal practice of having separate scalar ALUs and separate SIMD ALUs is not followed.
 
 Instead a suite of "partition points" identical in fashion to the Aspex Microelectronics ASP (Array-String-Architecture) architecture is deployed.
+These "breaks" may be set at runtime at any time.
 
 Basic principle: when all partition gates are open the ALU is subdivided into isolated and independent 8 bit SIMD ALUs.  Whenever any one gate is opened, the relevant 8 bit "part-results" are chained together in a downstream cascade to create 16 bit, 32 bit, 64 bit and 128 bit compound results.