i965: Shorten context base class dereference chains.

ctx->DrawBuffer is much more sensible than brw->intel.ctx.DrawBuffer.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 7203802f91303e2d8df88df8d2863f9ea82d4761..c9137cfd7e7da7769642d9ae23c10a9244c75d47 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -875,7 +875,7 @@ static void upload_polygon_stipple_offset(struct brw_context *brw)
     * to a user-created FBO then our native pixel coordinate system
     * works just fine, and there's no window system to worry about.
     */
-   if (_mesa_is_winsys_fbo(brw->intel.ctx.DrawBuffer))
+   if (_mesa_is_winsys_fbo(ctx->DrawBuffer))
       OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31);
    else
       OUT_BATCH(0);

diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 6515e28cf57f28506cf72b8d7a7e8001bd8c5ce8..86fee6a47b2a20f48532391bd4436cfb3cbd8e31 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -131,7 +131,7 @@ static void upload_sf_unit( struct brw_context *brw )
    struct brw_sf_unit_state *sf;
    drm_intel_bo *bo = brw->batch.bo;
    int chipset_max_threads;
-   bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);
+   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
 
    sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
                        sizeof(*sf), 64, &brw->sf.state_offset);

diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 29ff0f8f289eb5dc31261e1db1ad1ce01df1367e..76d1317cec8e989e64ad6be7a671735c8cc01891 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -135,7 +135,7 @@ upload_sf_state(struct brw_context *brw)
    uint32_t dw1, dw2, dw3, dw4, dw16, dw17;
    int i;
    /* _NEW_BUFFER */
-   bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);
+   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
    bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
 
    int attr = 0, input_index = 0;

diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 31d87a477a48248a5e2a13e244562a8b0d45dd69..a5e7cc98fb86fe27581ffec3112d16457b1d4441 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -99,7 +99,7 @@ const struct brw_tracked_state gen6_vs_push_constants = {
 static void
 upload_vs_state(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
+   struct gl_context *ctx = &brw->intel.ctx;
    uint32_t floating_point_mode = 0;
 
    /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section
@@ -139,7 +139,7 @@ upload_vs_state(struct brw_context *brw)
    /* Use ALT floating point mode for ARB vertex programs, because they
     * require 0^0 == 1.
     */
-   if (intel->ctx.Shader.CurrentVertexProgram == NULL)
+   if (ctx->Shader.CurrentVertexProgram == NULL)
       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
 
    BEGIN_BATCH(6);

diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index 5ebe6f293d0934f465708413d6d20f07ccbe2763..d72ee02ccf537ca01c02cfbb3ea1e7f1f7c10166 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -163,7 +163,7 @@ upload_sf_state(struct brw_context *brw)
    uint32_t dw1, dw2, dw3;
    float point_size;
    /* _NEW_BUFFERS */
-   bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);
+   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
    bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
 
    dw1 = GEN6_SF_STATISTICS_ENABLE |

diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 1fad26020050e7c4ffdcf45867aa060c6cef4e85..6c16a9d4850d37396fc830a59ad2df8ffde56886 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -32,7 +32,7 @@
 static void
 upload_vs_state(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
+   struct gl_context *ctx = &brw->intel.ctx;
    uint32_t floating_point_mode = 0;
    const int max_threads_shift = brw->intel.is_haswell ?
       HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT;
@@ -80,7 +80,7 @@ upload_vs_state(struct brw_context *brw)
    /* Use ALT floating point mode for ARB vertex programs, because they
     * require 0^0 == 1.
     */
-   if (intel->ctx.Shader.CurrentVertexProgram == NULL)
+   if (ctx->Shader.CurrentVertexProgram == NULL)
       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
 
    BEGIN_BATCH(6);

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index b0255513cf4ac4d1a9f6371676b82abfafccfac2..8ae7aeac873c52b9979eab033eac98135eeb19a8 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -115,7 +115,7 @@ upload_ps_state(struct brw_context *brw)
    struct intel_context *intel = &brw->intel;
    struct gl_context *ctx = &intel->ctx;
    uint32_t dw2, dw4, dw5;
-   const int max_threads_shift = brw->intel.is_haswell ?
+   const int max_threads_shift = intel->is_haswell ?
       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 
    /* BRW_NEW_PS_BINDING_TABLE */
@@ -169,7 +169,7 @@ upload_ps_state(struct brw_context *brw)
     * rendering, CurrentFragmentProgram is used for this check to
     * differentiate between the GLSL and non-GLSL cases.
     */
-   if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
+   if (ctx->Shader.CurrentFragmentProgram == NULL)
       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 
    if (intel->is_haswell)

diff --git a/src/mesa/drivers/dri/i965/intel_buffers.c b/src/mesa/drivers/dri/i965/intel_buffers.c
index b5fb33831f3f15d0197829385104d09aa25082b6..4ee5a8fc2c9aa5575c54957d253f9837533d327b 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_buffers.c
+++ b/src/mesa/drivers/dri/i965/intel_buffers.c
@@ -41,8 +41,8 @@
 void
 intel_check_front_buffer_rendering(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   const struct gl_framebuffer *fb = intel->ctx.DrawBuffer;
+   struct gl_context *ctx = &brw->intel.ctx;
+   const struct gl_framebuffer *fb = ctx->DrawBuffer;
    if (_mesa_is_winsys_fbo(fb)) {
       /* drawing to window system buffer */
       if (fb->_NumColorDrawBuffers > 0) {

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index eccba84c273c491c0b8542a8fd6fcc9c8634d599..47fd53e6fefc9a0bfce99da51814a44c85a34ae5 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -162,8 +162,7 @@ intelInitExtensions(struct gl_context *ctx)
    if (ctx->API != API_OPENGL_CORE)
       ctx->Extensions.ARB_color_buffer_float = true;
 
-   if (intel->ctx.Mesa_DXTn
-       || driQueryOptionb(&brw->optionCache, "force_s3tc_enable"))
+   if (ctx->Mesa_DXTn || driQueryOptionb(&brw->optionCache, "force_s3tc_enable"))
       ctx->Extensions.EXT_texture_compression_s3tc = true;
 
    ctx->Extensions.ANGLE_texture_compression_dxt = true;

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 44f692099b37aed1a60b1b3c0d5c532a608b5e48..d443402aa7b7dc246d784ac0780b729d64d3895c 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -204,9 +204,9 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
        * except they're less useful because you can't texture with
        * them.
        */
-      rb->Format = intel->ctx.Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D,
-                                                        internalFormat,
-                                                        GL_NONE, GL_NONE);
+      rb->Format = ctx->Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D,
+                                                   internalFormat,
+                                                   GL_NONE, GL_NONE);
       break;
    case GL_STENCIL_INDEX:
    case GL_STENCIL_INDEX1_EXT:
@@ -879,15 +879,15 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
 void
 intel_fbo_init(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   intel->ctx.Driver.NewFramebuffer = intel_new_framebuffer;
-   intel->ctx.Driver.NewRenderbuffer = intel_new_renderbuffer;
-   intel->ctx.Driver.MapRenderbuffer = intel_map_renderbuffer;
-   intel->ctx.Driver.UnmapRenderbuffer = intel_unmap_renderbuffer;
-   intel->ctx.Driver.RenderTexture = intel_render_texture;
-   intel->ctx.Driver.FinishRenderTexture = intel_finish_render_texture;
-   intel->ctx.Driver.ValidateFramebuffer = intel_validate_framebuffer;
-   intel->ctx.Driver.BlitFramebuffer = intel_blit_framebuffer;
-   intel->ctx.Driver.EGLImageTargetRenderbufferStorage =
+   struct dd_function_table *dd = &brw->intel.ctx.Driver;
+   dd->NewFramebuffer = intel_new_framebuffer;
+   dd->NewRenderbuffer = intel_new_renderbuffer;
+   dd->MapRenderbuffer = intel_map_renderbuffer;
+   dd->UnmapRenderbuffer = intel_unmap_renderbuffer;
+   dd->RenderTexture = intel_render_texture;
+   dd->FinishRenderTexture = intel_finish_render_texture;
+   dd->ValidateFramebuffer = intel_validate_framebuffer;
+   dd->BlitFramebuffer = intel_blit_framebuffer;
+   dd->EGLImageTargetRenderbufferStorage =
       intel_image_target_renderbuffer_storage;
 }

diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 15015dd6d064b259d239cceaf277b60abc3ba5a5..284fe800ee0e7699c1c85058c7beca6315981fff 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -113,7 +113,6 @@ try_pbo_upload(struct gl_context *ctx,
               GLenum format, GLenum type, const void *pixels)
 {
    struct intel_texture_image *intelImage = intel_texture_image(image);
-   struct intel_context *intel = intel_context(ctx);
    struct brw_context *brw = brw_context(ctx);
    struct intel_buffer_object *pbo = intel_buffer_object(unpack->BufferObj);
    GLuint src_offset;
@@ -124,8 +123,7 @@ try_pbo_upload(struct gl_context *ctx,
 
    DBG("trying pbo upload\n");
 
-   if (intel->ctx._ImageTransferState ||
-       unpack->SkipPixels || unpack->SkipRows) {
+   if (ctx->_ImageTransferState || unpack->SkipPixels || unpack->SkipRows) {
       DBG("%s: image transfer\n", __FUNCTION__);
       return false;
    }

diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index 3665119d084ca33a60dedd219bbf8d1dbbdeb74e..77b657108968a3820667b8223fae9982e2c8410a 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -42,7 +42,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
 {
    struct intel_context *intel = &brw->intel;
    struct gl_context *ctx = &intel->ctx;
-   struct gl_texture_object *tObj = intel->ctx.Texture.Unit[unit]._Current;
+   struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
    struct intel_texture_object *intelObj = intel_texture_object(tObj);
    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
    GLuint face, i;