Do not re-sort box_module ports

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 25de7dababd132b15116bcbc6ec7f9f85a1c1dd6..efdd1844bd39d68583bed5c291f65b6e65e12438 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -739,10 +739,12 @@ struct XAigerWriter
                                if (box_module->get_bool_attribute("\\whitebox"))
                                        holes_cell = holes_module->addCell(cell->name, cell->type);
 
-                               RTLIL::Wire *holes_wire;
-                               // TODO: Only sort once
-                               box_module->wires_.sort(RTLIL::sort_by_id_str());
-                               for (const auto w : box_module->wires()) {
+                               // NB: Assume box_module->ports are sorted alphabetically
+                               //     (as RTLIL::Module::fixup_ports() would do)
+                               for (const auto &port_name : box_module->ports) {
+                                       RTLIL::Wire *w = box_module->wire(port_name);
+                                       log_assert(w);
+                                       RTLIL::Wire *holes_wire;
                                        RTLIL::SigSpec port_wire;
                                        if (w->port_input) {
                                                for (int i = 0; i < GetSize(w); i++) {