added english language description for lhzsux instruction

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index dfef1d51d743c66052ef72989f5e863a89c429b0..8e7283e6fd1329db61558c814eafb8475bc34573 100644 (file)
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -99,8 +99,6 @@ Description:
     The halfword in storage addressed by EA is loaded into
     RT[48:63]. RT[0:47] are set to 0.
 
-
-
 Special Registers Altered:
 
     None
@@ -117,6 +115,18 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and (RA).
+
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None