+2015-09-29 Jeff Law <law@redhat.com>
+
+ * config/sh/sh.c (gen_shl_and): Fix undefined left shift
+ behaviour.
+ (gen_shl_sext): Likewise.
+ * config/sh/sh.md (divsi3): Likewise.
+ (imm->ext_dest_operand splitter): Likewise.
+
2015-09-29 Sebastian Pop <s.pop@samsung.com>
Aditya Kumar <aditya.k7@samsung.com>
that don't matter. This way, we might be able to get a shorter
signed constant. */
if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
- mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
+ mask |= (HOST_WIDE_INT) ((HOST_WIDE_INT_M1U) << (31 - total_shift));
case 2:
/* Don't expand fine-grained when combining, because that will
make the pattern fail. */
}
emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
- emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
+ emit_insn (gen_addsi3 (dest, dest, GEN_INT (HOST_WIDE_INT_M1U << (insize - 1))));
operands[0] = dest;
operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
gen_shifty_op (ASHIFT, operands);
tab_base = force_reg (DImode, tab_base);
}
if (TARGET_DIVIDE_INV20U)
- i2p27 = force_reg (DImode, GEN_INT (-2 << 27));
+ i2p27 = force_reg (DImode, GEN_INT ((unsigned HOST_WIDE_INT)-2 << 27));
else
i2p27 = GEN_INT (0);
if (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)
break;
}
/* Try movi / mshflo.l w/ r63. */
- val2 = val + ((HOST_WIDE_INT) -1 << 32);
+ val2 = val + ((HOST_WIDE_INT) (HOST_WIDE_INT_M1U << 32));
if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
{
operands[1] = gen_mshflo_l_di (operands[0], operands[0],