re PR target/80799 (x86-32 bits generates MMX without EMMS)

	PR target/80799
	* config/i386/mmx.md (*mov<mode>_internal): Enable
	alternatives 11, 12, 13 and 14 also for 32bit targets.
	Remove alternatives 15, 16, 17 and 18.
	* config/i386/sse.md (vec_concatv2di): Change
	alternative (!x, *y) to (x, ?!*Yn).

testsuite/ChangeLog:

	PR target/80799
	* g++.dg/other/i386-11.C: New test.

From-SVN: r248246

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a90c8880532616eb06b79ee76716b1e7f2a63bfa..0299a550ac41b85bf70e3dd87108a1f598a9f61d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2017-05-18  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/80799
+       * config/i386/mmx.md (*mov<mode>_internal): Enable
+       alternatives 11, 12, 13 and 14 also for 32bit targets.
+       Remove alternatives 15, 16, 17 and 18.
+       * config/i386/sse.md (vec_concatv2di): Change
+       alternative (!x, *y) to (x, ?!*Yn).
+
 2017-05-18  Paolo Carlini  <paolo.carlini@oracle.com>
 
        * dumpfile.h (enum dump_kind): Remove stray comma.
@@ -280,7 +289,7 @@
 
 2017-05-16  Uros Bizjak  <ubizjak@gmail.com>
 
-       * config/i386.i386.md (*movsi_internal): Split (?rm,*y) alternative
+       * config/i386/i386.md (*movsi_internal): Split (?rm,*y) alternative
        to (?r,*Yn) and (?m,*y) alternatives, and (?*y,rm) to (?*Ym,r)
        and (?*y,m).  Update insn attributes.
 

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 68972bb45c90506ec0d208ef6b414e257ba51d2f..7a1789f0b473f5dbe63547bcf151e8ae0b2b745e 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -78,9 +78,9 @@
 
 (define_insn "*mov<mode>_internal"
   [(set (match_operand:MMXMODE 0 "nonimmediate_operand"
-    "=r ,o ,r,r ,m ,?!y,!y,?!y,m  ,r   ,?!Ym,v,v,v,m,*x,*x,*x,m ,r ,Yi,!Ym,*Yi")
+    "=r ,o ,r,r ,m ,?!y,!y,?!y,m  ,r   ,?!Ym,v,v,v,m,r ,Yi,!Ym,*Yi")
        (match_operand:MMXMODE 1 "vector_move_operand"
-    "rCo,rC,C,rm,rC,C  ,!y,m  ,?!y,?!Yn,r   ,C,v,m,v,C ,*x,m ,*x,Yj,r ,*Yj,!Yn"))]
+    "rCo,rC,C,rm,rC,C  ,!y,m  ,?!y,?!Yn,r   ,C,v,m,v,Yj,r ,*Yj,!Yn"))]
   "TARGET_MMX
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
 {
@@ -146,7 +146,7 @@
   [(set (attr "isa")
      (cond [(eq_attr "alternative" "0,1")
              (const_string "nox64")
-           (eq_attr "alternative" "2,3,4,9,10,11,12,13,14,19,20")
+           (eq_attr "alternative" "2,3,4,9,10,15,16")
              (const_string "x64")
           ]
           (const_string "*")))
@@ -159,14 +159,14 @@
              (const_string "mmx")
            (eq_attr "alternative" "6,7,8,9,10")
              (const_string "mmxmov")
-           (eq_attr "alternative" "11,15")
+           (eq_attr "alternative" "11")
              (const_string "sselog1")
-           (eq_attr "alternative" "21,22")
+           (eq_attr "alternative" "17,18")
              (const_string "ssecvt")
           ]
           (const_string "ssemov")))
    (set (attr "prefix_rex")
-     (if_then_else (eq_attr "alternative" "9,10,19,20")
+     (if_then_else (eq_attr "alternative" "9,10,15,16")
        (const_string "1")
        (const_string "*")))
    (set (attr "prefix")
@@ -181,7 +181,7 @@
    (set (attr "mode")
      (cond [(eq_attr "alternative" "2")
              (const_string "SI")
-           (eq_attr "alternative" "11,12,15,16")
+           (eq_attr "alternative" "11,12")
              (cond [(ior (match_operand 0 "ext_sse_reg_operand")
                          (match_operand 1 "ext_sse_reg_operand"))
                        (const_string "XI")
@@ -197,7 +197,7 @@
                    ]
                    (const_string "TI"))
 
-           (and (eq_attr "alternative" "13,14,17,18")
+           (and (eq_attr "alternative" "13,14")
                 (ior (match_test "<MODE>mode == V2SFmode")
                      (not (match_test "TARGET_SSE2"))))
              (const_string "V2SF")

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index ff91c45d4953d6ee5222ae4dbd7297d4ac65b298..7f27ca854efeabcddf2350cab4a229a017e6d4a1 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -13863,10 +13863,10 @@
 ;; movd instead of movq is required to handle broken assemblers.
 (define_insn "vec_concatv2di"
   [(set (match_operand:V2DI 0 "register_operand"
-         "=Yr,*x,x ,v ,Yi,v ,!x,x,v ,x,x,v")
+         "=Yr,*x,x ,v ,Yi,v ,x    ,x,v ,x,x,v")
        (vec_concat:V2DI
          (match_operand:DI 1 "nonimmediate_operand"
-         "  0, 0,x ,Yv,r ,vm,*y,0,Yv,0,0,v")
+         "  0, 0,x ,Yv,r ,vm,?!*Yn,0,Yv,0,0,v")
          (match_operand:DI 2 "vector_move_operand"
          "*rm,rm,rm,rm,C ,C ,C ,x,Yv,x,m,m")))]
   "TARGET_SSE"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d20ade3afcd9e11b66aae501d9a1997c4b730f4d..60299f2c8c1c2a4465c1cf6284d303ec656669a0 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2017-05-18  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/80799
+       * g++.dg/other/i386-11.C: New test.
+
 2017-05-18  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
        * fold-vec-div-float.c: Update dg-requires and dg-options statements.

diff --git a/gcc/testsuite/g++.dg/other/i386-11.C b/gcc/testsuite/g++.dg/other/i386-11.C
new file mode 100644 (file)
index 0000000..8e06617
--- /dev/null
+++ b/gcc/testsuite/g++.dg/other/i386-11.C
@@ -0,0 +1,57 @@
+// PR target/80799
+// { dg-do compile { target i?86-*-* x86_64-*-* } }
+// { dg-require-effective-target c++11 }
+// { dg-options "-O2 -msse2" }
+
+#include <xmmintrin.h>
+#include <emmintrin.h>
+
+class alignas(16) GSVector4i
+{
+public:
+    __m128i m;
+
+       explicit GSVector4i(__m128i m)
+       {
+               this->m = m;
+       }
+
+       static void storel(void* p, const GSVector4i& v)
+       {
+               _mm_storel_epi64((__m128i*)p, v.m);
+       }
+
+       static GSVector4i loadl(const void* p)
+       {
+               return GSVector4i(_mm_loadl_epi64((__m128i*)p));
+       }
+
+       bool eq(const GSVector4i& v) const
+       {
+               return _mm_movemask_epi8(_mm_cmpeq_epi32(m, v.m)) == 0xffff;
+       }
+};
+
+
+union GIFRegTRXPOS
+{
+       unsigned long long u64;
+       void operator = (const GSVector4i& v) {GSVector4i::storel(this, v);}
+       bool operator != (const union GIFRegTRXPOS& r) const {return !((GSVector4i)r).eq(*this);}
+       operator GSVector4i() const {return GSVector4i::loadl(this);}
+};
+
+extern void dummy_call();
+extern GIFRegTRXPOS TRXPOS;
+
+void GIFRegHandlerTRXPOS(const GIFRegTRXPOS&  p)
+{
+       if(p != TRXPOS)
+       {
+               dummy_call();
+       }
+
+       TRXPOS = (GSVector4i)p;
+}
+
+// { dg-final { scan-assembler-not "%mm" } }