(no commit message)

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 52e98cee01363d01a81774607113e70301e240e9..c6233de43177857e4c2a67ee81ba8849c128d736 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -168,28 +168,6 @@ Sub-vector elements are not be considered "Vertical". The vec2/3/4
 is to be considered as if the "single element".  Caveats exist for
 [[sv/mv.swizzle]] and [[sv/mv.vec]] when Pack/Unpack is enabled.
 
-**Predicate Masks**
-
-Registers used as Predicate Masks must *never* be altered by *any*
-instruction when Vertical-First is active.  If more than the available
-predicate registers are required (r3, r10, r30, CR Predicate Fields) then
-because Vertical-First is not that different from executing standard
-Scalar instructions,
-a simple branch-conditional test should be used instead of predication,
-exactly as would normally be done if SVP64 was not in use.
-Alternatively the `setvl` instruction may be called again with the `vf`
-flag set. This tells the hardware to re-assess the use of Predicates
-
-These rules allow Hardware implementors to choose to
-free up the connection
-between registers used as predicates and registers used for standard
-purposes: Hazards need not be created.
-
-Note that each of the registers may each be used as predicates,
-or they may be used for standard normal purposes. If mixed for
-both purposes when Vertical-First is active, the results of execution
-is `UNDEFINED`.
-
 # Pseudocode
 
     // instruction fields: