(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 1ed8582c2ed1dd2edc7c61be65da9773f9b18fb7..02d3df394c9686765e54c9404e616a5bf6c2d845 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -107,7 +107,6 @@ Otherwise the normal SV hardware for-loop applies.  The three registers each may
 
 ## RM-2P-1S1D
 
-
 | Field Name | Field bits | Description                                 |
 |------------|------------|----------------------------|
 | MASK_KIND  | `0`        | Execution Mask Kind                          |
@@ -122,6 +121,23 @@ Otherwise the normal SV hardware for-loop applies.  The three registers each may
 
 note in [[discussion]]: TODO, evaluate if 2nd SUBVL should be added.  conclusion: no.  2nd SUBVL makes no sense except for mv, and that is covered by [[mv.vec]]
 
+## RM-2P-2S1D
+
+The primary purpose for this encoding is for Twin Predication on LOAD and STORE operations.  see [[sv/ldst]] for detailed anslysis.
+
+| Field Name | Field bits | Description                                 |
+|------------|------------|----------------------------|
+| MASK_KIND  | `0`        | Execution Mask Kind                          |
+| MASK       | `1:3`      | Execution Mask                               |
+| ELWIDTH    | `4:5`      | Element Width                                |
+| SUBVL      | `6:7`      | Sub-vector length                           |
+| Rdest_EXTRA2 | `8:9`   | extra bits for Rdest (R\*_EXTRA2 Encoding)   |
+| Rsrc1_EXTRA2 | `10:11` | extra bits for Rsrc1 (R\*_EXTRA2 Encoding)   |
+| Rsrc2_EXTRA2 | `12:13` | extra bits for Rsrc2 (R\*_EXTRA2 Encoding)   |
+| MASK_SRC     | `14:16`    | Execution Mask for Source     |
+| ELWIDTH_SRC  | `17:18`    | Element Width for Source      |
+| MODE         | `19:23`    | see [[discussion]]                        |
+
 ## R\*_EXTRA2 and R\*_EXTRA3 Encoding
 
 (**TODO: 2-bit version of the table, just like in the original SVPrefix.  This is important, to save bits on 4-operand instructions such as fmadd**)