soc_core: additional csr_alignment follow-up fixes

- Update a few additional places to use DFII_ADDR_SHIFT instead of
  a hard-coded 4, which assumed 32-bit alignment.

- Force 64-bit alignment Rocket -- the only supported configuration!

This is a fixup for commit f4770219, tested on Rocket and 64bit Linux.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 00de250fa6c58eee9cbcc3fec42aaa3e15943e43..6f5b3cf7d58713cb7bee73b2a0aac9c3a347ce32 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -186,11 +186,14 @@ class SoCCore(Module):
 
         # Parameters managment ---------------------------------------------------------------------
 
-        # FIXME: RocketChip reserves the first 256Mbytes for internal use, change default mem_map
+        # NOTE: RocketChip reserves the first 256Mbytes for internal use,
+        #       so we must change default mem_map;
+        #       Also, CSRs *must* be 64-bit aligned.
         if cpu_type == "rocket":
             self.soc_mem_map["rom"]  = 0x10000000
             self.soc_mem_map["sram"] = 0x11000000
             self.soc_mem_map["csr"]  = 0x12000000
+            csr_alignment = 64
 
         if cpu_type == "None":
             cpu_type = None

diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 5cb4929d124206a23dc5df5f38f17eaa3e7e4a82..0af3e4fc6a0ca2f4e41ae0c85753037ecdaae904 100644 (file)
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -536,7 +536,7 @@ static void read_level(int module)
        /* Write test pattern */
        for(p=0;p<DFII_NPHASES;p++)
                for(i=0;i<DFII_PIX_DATA_SIZE;i++)
-                       MMPTR(sdram_dfii_pix_wrdata_addr[p]+4*i) = prs[DFII_PIX_DATA_SIZE*p+i];
+                       MMPTR(sdram_dfii_pix_wrdata_addr[p]+DFII_ADDR_SHIFT*i) = prs[DFII_PIX_DATA_SIZE*p+i];
        sdram_dfii_piwr_address_write(0);
        sdram_dfii_piwr_baddress_write(0);
        command_pwr(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);

diff --git a/litex/soc/software/libbase/id.c b/litex/soc/software/libbase/id.c
index d380f4976dd434467c194668cdcfff944f8c38e0..d2d7b513ac442684310375402205ee47673dcc92 100644 (file)
--- a/litex/soc/software/libbase/id.c
+++ b/litex/soc/software/libbase/id.c
@@ -4,13 +4,14 @@
 #include <string.h>
 #include <id.h>
 
+#define DFII_ADDR_SHIFT CONFIG_CSR_ALIGNMENT/8
 
 void get_ident(char *ident)
 {
 #ifdef CSR_IDENTIFIER_MEM_BASE
     int i;
     for(i=0;i<256;i++)
-        ident[i] = MMPTR(CSR_IDENTIFIER_MEM_BASE + 4*i);
+        ident[i] = MMPTR(CSR_IDENTIFIER_MEM_BASE + DFII_ADDR_SHIFT*i);
 #else
     ident[0] = 0;
 #endif