i965: Move intel_context::vtbl to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index f97e19a805facaa0b4c827ca450d08ad6d3ddf83..21894cdd89a59dda8c7099ee3fd3ab8f99953e72 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -763,6 +763,45 @@ struct brw_context
 {
    struct intel_context intel;  /**< base class, must be first field */
 
+   struct
+   {
+      void (*destroy) (struct brw_context * brw);
+      void (*finish_batch) (struct brw_context * brw);
+      void (*new_batch) (struct brw_context * brw);
+
+      void (*update_texture_surface)(struct gl_context *ctx,
+                                     unsigned unit,
+                                     uint32_t *binding_table,
+                                     unsigned surf_index);
+      void (*update_renderbuffer_surface)(struct brw_context *brw,
+                                         struct gl_renderbuffer *rb,
+                                         bool layered,
+                                         unsigned unit);
+      void (*update_null_renderbuffer_surface)(struct brw_context *brw,
+                                              unsigned unit);
+      void (*create_constant_surface)(struct brw_context *brw,
+                                     drm_intel_bo *bo,
+                                     uint32_t offset,
+                                     uint32_t size,
+                                     uint32_t *out_offset,
+                                      bool dword_pitch);
+
+      /**
+       * Send the appropriate state packets to configure depth, stencil, and
+       * HiZ buffers (i965+ only)
+       */
+      void (*emit_depth_stencil_hiz)(struct brw_context *brw,
+                                     struct intel_mipmap_tree *depth_mt,
+                                     uint32_t depth_offset,
+                                     uint32_t depthbuffer_format,
+                                     uint32_t depth_surface_type,
+                                     struct intel_mipmap_tree *stencil_mt,
+                                     bool hiz, bool separate_stencil,
+                                     uint32_t width, uint32_t height,
+                                     uint32_t tile_x, uint32_t tile_y);
+
+   } vtbl;
+
    /** drirc option cache */
    driOptionCache optionCache;
 

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 8d143be3c6e5ccf58f00aa4ff7677e48416b2d85..e7c14f05d04822a6691f1f5eb1a6d481cce99fc4 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -636,10 +636,10 @@ brw_emit_depthbuffer(struct brw_context *brw)
       height = stencil_irb->Base.Base.Height;
    }
 
-   intel->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
-                                      depthbuffer_format, depth_surface_type,
-                                      stencil_mt, hiz, separate_stencil,
-                                      width, height, tile_x, tile_y);
+   brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
+                                    depthbuffer_format, depth_surface_type,
+                                    stencil_mt, hiz, separate_stencil,
+                                    width, height, tile_x, tile_y);
 }
 
 void

diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index cbad0713bdedf29f577c93d07f2ec24f24e3acf1..1d70476e67398d3d54e70ff974ecb8b24055e357 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -91,8 +91,8 @@ brw_upload_vs_pull_constants(struct brw_context *brw)
    drm_intel_gem_bo_unmap_gtt(brw->vs.const_bo);
 
    const int surf = SURF_INDEX_VERT_CONST_BUFFER;
-   intel->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0, size,
-                                      &brw->vs.surf_offset[surf], false);
+   brw->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0, size,
+                                     &brw->vs.surf_offset[surf], false);
 
    brw->state.dirty.brw |= BRW_NEW_VS_CONSTBUF;
 }

diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index dadee9d365188e688e1c27d3bf4dface6afb3f1f..a4b8ed3194b1f80a3de1b1da3ca0e01e73618cd9 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -157,16 +157,16 @@ brw_new_batch(struct brw_context *brw)
 
 void brwInitVtbl( struct brw_context *brw )
 {
-   brw->intel.vtbl.new_batch = brw_new_batch;
-   brw->intel.vtbl.finish_batch = brw_finish_batch;
-   brw->intel.vtbl.destroy = brw_destroy_context;
+   brw->vtbl.new_batch = brw_new_batch;
+   brw->vtbl.finish_batch = brw_finish_batch;
+   brw->vtbl.destroy = brw_destroy_context;
 
    assert(brw->intel.gen >= 4);
    if (brw->intel.gen >= 7) {
       gen7_init_vtable_surface_functions(brw);
-      brw->intel.vtbl.emit_depth_stencil_hiz = gen7_emit_depth_stencil_hiz;
+      brw->vtbl.emit_depth_stencil_hiz = gen7_emit_depth_stencil_hiz;
    } else if (brw->intel.gen >= 4) {
       gen4_init_vtable_surface_functions(brw);
-      brw->intel.vtbl.emit_depth_stencil_hiz = brw_emit_depth_stencil_hiz;
+      brw->vtbl.emit_depth_stencil_hiz = brw_emit_depth_stencil_hiz;
    }
 }

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 16e3cc087d1ecd9756e1659221f344f258e1319d..38de064cc4833217fc9f0eb6f4a6573d800031a3 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -490,9 +490,9 @@ brw_upload_wm_pull_constants(struct brw_context *brw)
    }
    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 
-   intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0, size,
-                                      &brw->wm.surf_offset[surf_index],
-                                       true);
+   brw->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0, size,
+                                     &brw->wm.surf_offset[surf_index],
+                                     true);
 
    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 }
@@ -711,7 +711,6 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
 static void
 brw_update_renderbuffer_surfaces(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
    struct gl_context *ctx = &brw->intel.ctx;
    GLuint i;
 
@@ -720,14 +719,14 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw)
    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
         if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
-           intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
-                                                   ctx->DrawBuffer->Layered, i);
+           brw->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
+                                                  ctx->DrawBuffer->Layered, i);
         } else {
-           intel->vtbl.update_null_renderbuffer_surface(brw, i);
+           brw->vtbl.update_null_renderbuffer_surface(brw, i);
         }
       }
    } else {
-      intel->vtbl.update_null_renderbuffer_surface(brw, 0);
+      brw->vtbl.update_null_renderbuffer_surface(brw, 0);
    }
    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 }
@@ -780,9 +779,9 @@ brw_update_texture_surfaces(struct brw_context *brw)
 
          /* _NEW_TEXTURE */
          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
-            intel->vtbl.update_texture_surface(ctx, unit,
-                                               brw->vs.surf_offset,
-                                               SURF_INDEX_VS_TEXTURE(s));
+            brw->vtbl.update_texture_surface(ctx, unit,
+                                             brw->vs.surf_offset,
+                                             SURF_INDEX_VS_TEXTURE(s));
          }
       }
 
@@ -791,9 +790,9 @@ brw_update_texture_surfaces(struct brw_context *brw)
 
          /* _NEW_TEXTURE */
          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
-            intel->vtbl.update_texture_surface(ctx, unit,
-                                               brw->wm.surf_offset,
-                                               SURF_INDEX_TEXTURE(s));
+            brw->vtbl.update_texture_surface(ctx, unit,
+                                             brw->wm.surf_offset,
+                                             SURF_INDEX_TEXTURE(s));
          }
       }
    }
@@ -818,7 +817,6 @@ brw_upload_ubo_surfaces(struct brw_context *brw,
                        uint32_t *surf_offsets)
 {
    struct gl_context *ctx = &brw->intel.ctx;
-   struct intel_context *intel = &brw->intel;
 
    if (!shader)
       return;
@@ -835,10 +833,10 @@ brw_upload_ubo_surfaces(struct brw_context *brw,
        * glBindBufferRange case is undefined, we can just bind the whole buffer
        * glBindBufferBase wants and be a correct implementation.
        */
-      intel->vtbl.create_constant_surface(brw, bo, binding->Offset,
-                                         bo->size - binding->Offset,
-                                         &surf_offsets[i],
-                                          shader->Type == GL_FRAGMENT_SHADER);
+      brw->vtbl.create_constant_surface(brw, bo, binding->Offset,
+                                        bo->size - binding->Offset,
+                                        &surf_offsets[i],
+                                        shader->Type == GL_FRAGMENT_SHADER);
    }
 
    if (shader->NumUniformBlocks)
@@ -910,11 +908,9 @@ const struct brw_tracked_state brw_wm_binding_table = {
 void
 gen4_init_vtable_surface_functions(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-
-   intel->vtbl.update_texture_surface = brw_update_texture_surface;
-   intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
-   intel->vtbl.update_null_renderbuffer_surface =
+   brw->vtbl.update_texture_surface = brw_update_texture_surface;
+   brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
+   brw->vtbl.update_null_renderbuffer_surface =
       brw_update_null_renderbuffer_surface;
-   intel->vtbl.create_constant_surface = brw_create_constant_surface;
+   brw->vtbl.create_constant_surface = brw_create_constant_surface;
 }

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 1241656fe74926e3ff09c74e6b4870d3ddc82b96..c983abaa264f985a47be40bf19d505be25de08a8 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -632,11 +632,9 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
 void
 gen7_init_vtable_surface_functions(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-
-   intel->vtbl.update_texture_surface = gen7_update_texture_surface;
-   intel->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
-   intel->vtbl.update_null_renderbuffer_surface =
+   brw->vtbl.update_texture_surface = gen7_update_texture_surface;
+   brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
+   brw->vtbl.update_null_renderbuffer_surface =
       gen7_update_null_renderbuffer_surface;
-   intel->vtbl.create_constant_surface = gen7_create_constant_surface;
+   brw->vtbl.create_constant_surface = gen7_create_constant_surface;
 }

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 646b1f7571793fcdd38c75daa0e55e8b0ccf118b..0e71377cd2c955c2af8fd69c4b36b5bba8f82684 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -230,7 +230,7 @@ do_flush_locked(struct brw_context *brw)
       fprintf(stderr, "intel_do_flush_locked failed: %s\n", strerror(-ret));
       exit(1);
    }
-   intel->vtbl.new_batch(brw);
+   brw->vtbl.new_batch(brw);
 
    return ret;
 }
@@ -256,8 +256,8 @@ _intel_batchbuffer_flush(struct brw_context *brw,
 
    intel->batch.reserved_space = 0;
 
-   if (intel->vtbl.finish_batch)
-      intel->vtbl.finish_batch(brw);
+   if (brw->vtbl.finish_batch)
+      brw->vtbl.finish_batch(brw);
 
    /* Mark the end of the buffer. */
    intel_batchbuffer_emit_dword(brw, MI_BATCH_BUFFER_END);

diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 04ad48d248020ba37f46fa39468b06de41766ce1..73609921bafe580f2ff0f695da906b294767a817 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -622,7 +622,7 @@ intelDestroyContext(__DRIcontext * driContextPriv)
 
       _mesa_meta_free(&intel->ctx);
 
-      intel->vtbl.destroy(brw);
+      brw->vtbl.destroy(brw);
 
       if (ctx->swrast_context) {
          _swsetup_DestroyContext(&intel->ctx);

diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index f0ce63d698327ee0b148bdbc1200da18af9b8bb2..5ea17af53226b58dd931864eaef73142491f2151 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -113,45 +113,6 @@ struct intel_context
 {
    struct gl_context ctx;  /**< base class, must be first field */
 
-   struct
-   {
-      void (*destroy) (struct brw_context * brw);
-      void (*finish_batch) (struct brw_context * brw);
-      void (*new_batch) (struct brw_context * brw);
-
-      void (*update_texture_surface)(struct gl_context *ctx,
-                                     unsigned unit,
-                                     uint32_t *binding_table,
-                                     unsigned surf_index);
-      void (*update_renderbuffer_surface)(struct brw_context *brw,
-                                         struct gl_renderbuffer *rb,
-                                         bool layered,
-                                         unsigned unit);
-      void (*update_null_renderbuffer_surface)(struct brw_context *brw,
-                                              unsigned unit);
-      void (*create_constant_surface)(struct brw_context *brw,
-                                     drm_intel_bo *bo,
-                                     uint32_t offset,
-                                     uint32_t size,
-                                     uint32_t *out_offset,
-                                      bool dword_pitch);
-
-      /**
-       * Send the appropriate state packets to configure depth, stencil, and
-       * HiZ buffers (i965+ only)
-       */
-      void (*emit_depth_stencil_hiz)(struct brw_context *brw,
-                                     struct intel_mipmap_tree *depth_mt,
-                                     uint32_t depth_offset,
-                                     uint32_t depthbuffer_format,
-                                     uint32_t depth_surface_type,
-                                     struct intel_mipmap_tree *stencil_mt,
-                                     bool hiz, bool separate_stencil,
-                                     uint32_t width, uint32_t height,
-                                     uint32_t tile_x, uint32_t tile_y);
-
-   } vtbl;
-
    GLuint NewGLState;
  
    dri_bufmgr *bufmgr;