(no commit message)

diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index 8278f53e54f63ce6dc05e82536cd8f399e0c625a..8bf6a42cf1485301714adf9934144b627265184f 100644 (file)
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -24,17 +24,21 @@ All implementations regardless of back-end capability may execute the exact
 same binaries *(this is known to be extremely important to the Power ISA
 ecosystem)*.
 
-Simple-V is **not RISC-V and is not RISC-V Vectors**. NEC SX Aurora,
-RVV and Simple-V are all based on Cray-style Vectors hence the similarity,
-the provision of a `setvl` instruction and why they are each called
-"Scalable" Vectors because it is the `setvl` instruction that
-presents the programmer with explicit control over Vector length.
+Simple-V is **not RISC-V and is not RISC-V Vectors**.
+[NEC SX Aurora](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf),
+[RVV](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc), [Simple-V](https://ftp.libre-soc.org/simple_v_spec.pdf) and
+[MRISC32](https://github.com/mrisc32/mrisc32)
+are all based on Cray-style Scalable Vectors
+of 30 years ago, hence the similarity,
+the provision of a `setvl` instruction, and why they are each called
+"Scalable" Vectors, because it is the `setvl` instruction that
+presents the **programmer** with explicit control over Vector length.
 
 ARM NEON, AVX-512 and ARM SVE2 are all Predicated SIMD ISAs and
-**do not provide Scalability to the Programmer** (SVE2 is **Silicon**
+**do not provide Scalability to the Programmer**.  SVE2 is **Silicon**
 Scalable, not **Programmer** Scalable: the distinction is profoundly
-important).
-For Predicated SIMD, Programmers must emulate scaling
+important.
+For Predicated SIMD, Programmers must emulate Cray-style scaling
 through explicit predicate masking, which increases instruction count in
 hot-loops.