r300: move depth output rewrite out of NQSSADCE
authorMaciej Cencora <m.cencora@gmail.com>
Sat, 4 Jul 2009 14:50:25 +0000 (16:50 +0200)
committerMaciej Cencora <m.cencora@gmail.com>
Mon, 13 Jul 2009 17:25:59 +0000 (19:25 +0200)
src/mesa/drivers/dri/r300/r300_fragprog_common.c
src/mesa/drivers/dri/r300/radeon_nqssadce.c
src/mesa/drivers/dri/r300/radeon_nqssadce.h

index e90be9b7f852df18c9b07f434d16b7bbc21111e1..d5ef18b2ad8bfaf5c9e675c43373d89f0d70cafb 100644 (file)
@@ -239,6 +239,46 @@ static void build_state(
        }
 }
 
+static void rewrite_depth_out(struct gl_program *prog)
+{
+       struct prog_instruction *inst;
+
+       for (inst = prog->Instructions; inst->Opcode != OPCODE_END; ++inst) {
+               if (inst->DstReg.File != PROGRAM_OUTPUT || inst->DstReg.Index != FRAG_RESULT_DEPTH)
+                       continue;
+
+               if (inst->DstReg.WriteMask & WRITEMASK_Z) {
+                       inst->DstReg.WriteMask = WRITEMASK_W;
+               } else {
+                       inst->DstReg.WriteMask = 0;
+                       continue;
+               }
+
+               switch (inst->Opcode) {
+                       case OPCODE_FRC:
+                       case OPCODE_MOV:
+                               inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]);
+                               break;
+                       case OPCODE_ADD:
+                       case OPCODE_MAX:
+                       case OPCODE_MIN:
+                       case OPCODE_MUL:
+                               inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]);
+                               inst->SrcReg[1] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[1]);
+                               break;
+                       case OPCODE_CMP:
+                       case OPCODE_MAD:
+                               inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]);
+                               inst->SrcReg[1] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[1]);
+                               inst->SrcReg[2] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[2]);
+                               break;
+                       default:
+                               // Scalar instructions needn't be reswizzled
+                               break;
+               }
+       }
+}
+
 void r300TranslateFragmentShader(GLcontext *ctx, struct r300_fragment_program *fp)
 {
        r300ContextPtr r300 = R300_CONTEXT(ctx);
@@ -260,6 +300,8 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct r300_fragment_program *f
 
        rewriteFog(&compiler);
 
+       rewrite_depth_out(compiler.program);
+
        if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
                struct radeon_program_transformation transformations[] = {
                        { &r500_transform_TEX, &compiler },
@@ -287,16 +329,14 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct r300_fragment_program *f
                struct radeon_nqssadce_descr nqssadce = {
                        .Init = &nqssadce_init,
                        .IsNativeSwizzle = &r500FPIsNativeSwizzle,
-                       .BuildSwizzle = &r500FPBuildSwizzle,
-                       .RewriteDepthOut = GL_TRUE
+                       .BuildSwizzle = &r500FPBuildSwizzle
                };
                radeonNqssaDce(ctx, compiler.program, &nqssadce);
        } else {
                struct radeon_nqssadce_descr nqssadce = {
                        .Init = &nqssadce_init,
                        .IsNativeSwizzle = &r300FPIsNativeSwizzle,
-                       .BuildSwizzle = &r300FPBuildSwizzle,
-                       .RewriteDepthOut = GL_TRUE
+                       .BuildSwizzle = &r300FPBuildSwizzle
                };
                radeonNqssaDce(ctx, compiler.program, &nqssadce);
        }
index d2591fa1bd2e9d462df9943bd07abea3695fb9e7..82dfc31dd0f865db418de5f2e1157ba409b8370f 100644 (file)
@@ -56,7 +56,7 @@ static struct register_state *get_reg_state(struct nqssadce_state* s, GLuint fil
  *
  * @note Works correctly only for X, Y, Z, W swizzles, not for constant swizzles.
  */
-static struct prog_src_register lmul_swizzle(GLuint swizzle, struct prog_src_register srcreg)
+struct prog_src_register lmul_swizzle(GLuint swizzle, struct prog_src_register srcreg)
 {
        struct prog_src_register tmp = srcreg;
        int i;
@@ -121,40 +121,6 @@ static struct prog_instruction* track_used_srcreg(struct nqssadce_state* s,
        return inst;
 }
 
-
-static void rewrite_depth_out(struct prog_instruction *inst)
-{
-       if (inst->DstReg.WriteMask & WRITEMASK_Z) {
-               inst->DstReg.WriteMask = WRITEMASK_W;
-       } else {
-               inst->DstReg.WriteMask = 0;
-               return;
-       }
-
-       switch (inst->Opcode) {
-       case OPCODE_FRC:
-       case OPCODE_MOV:
-               inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]);
-               break;
-       case OPCODE_ADD:
-       case OPCODE_MAX:
-       case OPCODE_MIN:
-       case OPCODE_MUL:
-               inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]);
-               inst->SrcReg[1] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[1]);
-               break;
-       case OPCODE_CMP:
-       case OPCODE_MAD:
-               inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]);
-               inst->SrcReg[1] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[1]);
-               inst->SrcReg[2] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[2]);
-               break;
-       default:
-               // Scalar instructions needn't be reswizzled
-               break;
-       }
-}
-
 static void unalias_srcregs(struct prog_instruction *inst, GLuint oldindex, GLuint newindex)
 {
        int nsrc = _mesa_num_inst_src_regs(inst->Opcode);
@@ -189,11 +155,6 @@ static void process_instruction(struct nqssadce_state* s)
                return;
 
        if (inst->Opcode != OPCODE_KIL) {
-               if (s->Descr->RewriteDepthOut) {
-                       if (inst->DstReg.File == PROGRAM_OUTPUT && inst->DstReg.Index == FRAG_RESULT_DEPTH)
-                               rewrite_depth_out(inst);
-               }
-
                struct register_state *regstate = get_reg_state(s, inst->DstReg.File, inst->DstReg.Index);
                if (!regstate) {
                        _mesa_problem(s->Ctx, "NqssaDce: bad destination register (%i[%i])\n",
index a4f94abcb62ea597cefba22fa22bcdb70e105110..e3341692e4f22140a12414bd93ca1c9aa682c39b 100644 (file)
@@ -83,14 +83,10 @@ struct radeon_nqssadce_descr {
         */
        void (*BuildSwizzle)(struct nqssadce_state*, struct prog_dst_register dst, struct prog_src_register src);
 
-       /**
-        * Rewrite instructions that write to DEPR.z to write to DEPR.w
-        * instead (rewriting is done *before* the WriteMask test).
-        */
-       GLboolean RewriteDepthOut;
        void *Data;
 };
 
 void radeonNqssaDce(GLcontext *ctx, struct gl_program *p, struct radeon_nqssadce_descr* descr);
+struct prog_src_register lmul_swizzle(GLuint swizzle, struct prog_src_register srcreg);
 
 #endif /* __RADEON_PROGRAM_NQSSADCE_H_ */