+2013-11-20 Walfred Tedeschi <walfred.tedeschi@intel.com>
+
+ * amd64-linux-nat.c (amd64_linux_gregset32_reg_offset):
+ Add MPX registers.
+ (amd64_linux_read_description): Add initialization for MPX and
+ AVX independently.
+ * amd64-linux-tdep.c: Includes features/i386/amd64-mpx-linux.c.
+ (amd64_linux_gregset_reg_offset): Add MPX registers.
+ (amd64_linux_core_read_description): Add initialization for MPX
+ registers.
+ (_initialize_amd64_linux_tdep): Initialize MPX targets.
+ * amd64-linux-tdep.h (AMD64_LINUX_RAX_REGNUM): Set it to the last
+ register on the list.
+ (tdesc_amd64_mpx_linux) Add new target for MPX.
+ * amd64-tdep.c: Includes features/i386/amd64-mpx.c.
+ (amd64_mpx_names): MPX register names.
+ (amd64_init_abi): Add MPX register while initializing the ABI.
+ (_initialize_amd64_tdep): Initialize MPX targets.
+ * amd64-tdep.h (amd64_regnum): Add MPX registers.
+ (AMD64_NUM_REGS): Set number of registers taking MPX into account.
+
2013-11-20 Walfred Tedeschi <walfred.tedeschi@intel.com>
* i386-linux-nat.c (GETXSTATEREGS_SUPPLIES): Add MPX
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
- ORIG_RAX * 8 /* "orig_eax" */
+ -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
+ -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
+ ORIG_RAX * 8, /* "orig_eax" */
};
\f
}
/* Check the native XCR0 only if PTRACE_GETREGSET is available. */
- if (have_ptrace_getregset
- && (xcr0 & I386_XSTATE_AVX_MASK) == I386_XSTATE_AVX_MASK)
+ if (have_ptrace_getregset && (xcr0 & I386_XSTATE_ALL_MASK))
{
- if (is_64bit)
+ switch (xcr0 & I386_XSTATE_ALL_MASK)
{
- if (is_x32)
- return tdesc_x32_avx_linux;
+ case I386_XSTATE_MPX_MASK:
+ if (is_64bit)
+ {
+ if (is_x32)
+ return tdesc_x32_avx_linux; /* No MPX on x32 using AVX. */
+ else
+ return tdesc_amd64_mpx_linux;
+ }
+ else
+ return tdesc_i386_mpx_linux;
+ case I386_XSTATE_AVX_MASK:
+ if (is_64bit)
+ {
+ if (is_x32)
+ return tdesc_x32_avx_linux;
+ else
+ return tdesc_amd64_avx_linux;
+ }
+ else
+ return tdesc_i386_avx_linux;
+ default:
+ if (is_64bit)
+ {
+ if (is_x32)
+ return tdesc_x32_linux;
+ else
+ return tdesc_amd64_linux;
+ }
else
- return tdesc_amd64_avx_linux;
+ return tdesc_i386_linux;
}
- else
- return tdesc_i386_avx_linux;
}
else
{
#include "features/i386/amd64-linux.c"
#include "features/i386/amd64-avx-linux.c"
+#include "features/i386/amd64-mpx-linux.c"
#include "features/i386/x32-linux.c"
#include "features/i386/x32-avx-linux.c"
-1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
+ -1, -1, /* MPX registers BNDCFGU and BNDSTATUS. */
15 * 8 /* "orig_rax" */
};
\f
{
/* Linux/x86-64. */
uint64_t xcr0 = i386_linux_core_read_xcr0 (abfd);
- switch ((xcr0 & I386_XSTATE_AVX_MASK))
+
+ switch (xcr0 & I386_XSTATE_ALL_MASK)
{
+ case I386_XSTATE_MPX_MASK:
+ if (gdbarch_ptr_bit (gdbarch) == 32)
+ return tdesc_x32_avx_linux; /* No x32 MPX falling back to AVX. */
+ else
+ return tdesc_amd64_mpx_linux;
case I386_XSTATE_AVX_MASK:
if (gdbarch_ptr_bit (gdbarch) == 32)
return tdesc_x32_avx_linux;
/* Initialize the Linux target description. */
initialize_tdesc_amd64_linux ();
initialize_tdesc_amd64_avx_linux ();
+ initialize_tdesc_amd64_mpx_linux ();
initialize_tdesc_x32_linux ();
initialize_tdesc_x32_avx_linux ();
}
/* Register number for the "orig_rax" register. If this register
contains a value >= 0 it is interpreted as the system call number
that the kernel is supposed to restart. */
-#define AMD64_LINUX_ORIG_RAX_REGNUM (AMD64_YMM15H_REGNUM + 1)
+#define AMD64_LINUX_ORIG_RAX_REGNUM (AMD64_BNDSTATUS_REGNUM + 1)
/* Total number of registers for GNU/Linux. */
#define AMD64_LINUX_NUM_REGS (AMD64_LINUX_ORIG_RAX_REGNUM + 1)
/* Linux target description. */
extern struct target_desc *tdesc_amd64_linux;
extern struct target_desc *tdesc_amd64_avx_linux;
+extern struct target_desc *tdesc_amd64_mpx_linux;
extern struct target_desc *tdesc_x32_linux;
extern struct target_desc *tdesc_x32_avx_linux;
#include "features/i386/amd64.c"
#include "features/i386/amd64-avx.c"
+#include "features/i386/amd64-mpx.c"
#include "features/i386/x32.c"
#include "features/i386/x32-avx.c"
"ymm12h", "ymm13h", "ymm14h", "ymm15h"
};
+static const char *amd64_mpx_names[] =
+{
+ "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
+};
+
/* DWARF Register Number Mapping as defined in the System V psABI,
section 3.6. */
tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
}
+ if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL)
+ {
+ tdep->mpx_register_names = amd64_mpx_names;
+ tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM;
+ tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
+ }
+
tdep->num_byte_regs = 20;
tdep->num_word_regs = 16;
tdep->num_dword_regs = 16;
{
initialize_tdesc_amd64 ();
initialize_tdesc_amd64_avx ();
+ initialize_tdesc_amd64_mpx ();
initialize_tdesc_x32 ();
initialize_tdesc_x32_avx ();
}
AMD64_XMM1_REGNUM, /* %xmm1 */
AMD64_MXCSR_REGNUM = AMD64_XMM0_REGNUM + 16,
AMD64_YMM0H_REGNUM, /* %ymm0h */
- AMD64_YMM15H_REGNUM = AMD64_YMM0H_REGNUM + 15
+ AMD64_YMM15H_REGNUM = AMD64_YMM0H_REGNUM + 15,
+ AMD64_BND0R_REGNUM = AMD64_YMM15H_REGNUM + 1,
+ AMD64_BND3R_REGNUM = AMD64_BND0R_REGNUM + 3,
+ AMD64_BNDCFGU_REGNUM,
+ AMD64_BNDSTATUS_REGNUM
};
/* Number of general purpose registers. */
#define AMD64_NUM_GREGS 24
-#define AMD64_NUM_REGS (AMD64_YMM15H_REGNUM + 1)
+#define AMD64_NUM_REGS (AMD64_BNDSTATUS_REGNUM + 1)
extern struct displaced_step_closure *amd64_displaced_step_copy_insn
(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,