Tiny fixes to verilog parser

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index feb810674d76bed66822ac8e0b09f64369735f04..94423366ee37953399212abfae1ebc6019ff6662 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -120,6 +120,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
                        if (node->type == AST_WIRE) {
                                if (this_wire_scope.count(node->str) > 0) {
                                        AstNode *first_node = this_wire_scope[node->str];
+                                       if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0)
+                                               goto wires_are_compatible;
                                        if (first_node->children.size() != node->children.size())
                                                goto wires_are_incompatible;
                                        for (size_t j = 0; j < node->children.size(); j++) {
@@ -138,6 +140,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
                                                goto wires_are_incompatible;
                                        if (first_node->port_id == 0 && (node->is_input || node->is_output))
                                                goto wires_are_incompatible;
+                               wires_are_compatible:
                                        if (node->is_input)
                                                first_node->is_input = true;
                                        if (node->is_output)

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 6e0b238e0af96614f37e9fb5020e21c75873d9fd..9caa236f8dad0e976948d77699e981b136d28200 100644 (file)
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -209,7 +209,12 @@ module:
        };
 
 module_para_opt:
-       '#' '(' TOK_PARAMETER param_decl_list optional_comma ')' | /* empty */;
+       '#' '(' module_para_list ')' | /* empty */;
+
+module_para_list:
+       TOK_PARAMETER single_param_decl |
+       TOK_PARAMETER single_param_decl ',' module_para_list |
+       /* empty */;
 
 module_args_opt:
        '(' ')' | /* empty */ | '(' module_args optional_comma ')';