Theoretically support trigger timing.

diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc
index 21609c87142e23364bb97df896748af16f88c7b1..c30b6bc11b448d0f3f96362d800348aad0b7eec0 100644 (file)
--- a/riscv/gdbserver.cc
+++ b/riscv/gdbserver.cc
@@ -1104,6 +1104,9 @@ class hardware_breakpoint_insert_op_t : public operation_t
               mcontrol = set_field(mcontrol, MCONTROL_EXECUTE, bp.execute);
               mcontrol = set_field(mcontrol, MCONTROL_LOAD, bp.load);
               mcontrol = set_field(mcontrol, MCONTROL_STORE, bp.store);
+              if (bp.load)
+                mcontrol = set_field(mcontrol, MCONTROL_TIMING, 1);
+
               gs.dr_write(SLOT_DATA1, mcontrol);
               state = STATE_WRITE_ADDRESS;
             } else {

diff --git a/riscv/mmu.h b/riscv/mmu.h
index 614ffc44c142e8df7690c8b99db13ddcc13766ad..3da2c92e9773742897b5898582c8fb73370a5d08 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -222,6 +222,9 @@ private:
     int match = proc->trigger_match(operation, address, data);
     if (match == -1)
       return NULL;
+    if (proc->state.mcontrol[match].timing == 0) {
+      throw trigger_matched_t(match, operation, address, data);
+    }
     return new trigger_matched_t(match, operation, address, data);
   }
 

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 57823f536a0f4c9d808635c20fa54ba627314fbd..e1f132e8b66ab11ba38c48f273bd1a50133bd77c 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -406,6 +406,10 @@ void processor_t::set_csr(int which, reg_t val)
         mc->store = get_field(val, MCONTROL_STORE);
         mc->load = get_field(val, MCONTROL_LOAD);
         // Assume we're here because of csrw.
+        if (mc->execute)
+          mc->timing = 0;
+        if (mc->load)
+          mc->timing = 1;
         trigger_updated();
       }
       break;