targets/ulx3s: use CAS latency of 3 to be compatible with production boards

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 40503bad99dad0cf7e35bbdb3472f8353ce6b20d..f3a3aac060a0da547960c9e3792d3de1b9e38f78 100755 (executable)
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -59,7 +59,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
         if not self.integrated_main_ram_size:
-            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
+            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=3)
             sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
             self.register_sdram(self.sdrphy,
                                 sdram_module.geom_settings,