(no commit message)

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index c9b8206221f7a7741e7d4d09f64485f2fe87d0b2..47fd91076e077f72f946d521e3d644be5ad97817 100644 (file)
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -21,6 +21,12 @@ Summary of Compliancy Levels, each Level includes all lower levels:
 
 * **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE
   into SVSRR1. Register Files as Standard Power ISA.
-* **Embedded**: `svstep` instruction, all SV Branch instructions,
+* **Embedded**: `svstep` instruction,
   and support for Hardware for-looping
   in both Horizontal-First and Vertical-First Mode as well as Predication
+  (Single and Twin)
+* **DSP/VPU**: 128 registers, all SV Branch instructions,
+  crweird instructions, element-width
+  overrides, and all Modes (Saturation, Fail-First, Predicate-Result,
+  Mapreduce/Iteration)
+* **3D/Advanced/Supercomputing**: REMAP capability