soc_core: fix cpu_variant renaming regression

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 8d4dd8a833014df68ffb617c7fb6a07413d9420b..0d59924e344758ebaf8b527d67937389908382d1 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -120,14 +120,14 @@ class SoCCore(LiteXSoC):
         self.config      = {}
 
         # Parameters management --------------------------------------------------------------------
-        if cpu_type == "None":
-            cpu_type = None
+        cpu_type    = None if cpu_type == "None" else cpu_type
+        cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
 
         if not with_wishbone:
             self.mem_map["csr"]  = 0x00000000
 
         self.cpu_type                   = cpu_type
-        self.cpu_variant                = cpu.check_format_cpu_variant(cpu_variant)
+        self.cpu_variant                = cpu_variant
 
         self.integrated_rom_size        = integrated_rom_size
         self.integrated_rom_initialized = integrated_rom_init != []