Fixed wrong declaration in Verilog backend
authordh73 <dh73_fpga@qq.com>
Sun, 1 Oct 2017 16:11:32 +0000 (11:11 -0500)
committerdh73 <dh73_fpga@qq.com>
Sun, 1 Oct 2017 16:11:32 +0000 (11:11 -0500)
backends/verilog/verilog_backend.cc

index 33f9a81e4a87cf62357b8ddf932c6ab97d90bfdf..48e06dc7ca982040d9ef0e86dfb58729cfb1eefa 100644 (file)
@@ -175,7 +175,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
                        if (set_signed && val < 0)
                                f << stringf("-32'sd%u", -val);
                        else {
-                                if(!nobasenradix)
+                                if(nobasenradix)
                                   f << stringf("%u", val); // There's no signed parameter on megawizard IP 
                                 else
                                        f << stringf("32'%sd%u", set_signed ? "s" : "", val);
@@ -1585,8 +1585,8 @@ struct VerilogBackend : public Backend {
                                continue;
                        }
                         if (arg == "-nobasenradix") {
-                          defparam = true;
-                          continue;
+                                nobasenradix = true;
+                                continue;
                        }
                        if (arg == "-blackboxes") {
                                blackboxes = true;