* Possibility to encapsulate legacy Verilog/VHDL code.
* Complex FPGA cores that can be used integrated in MiSoC or standalone:
- LiteEth: a small footprint and configurable Ethernet core
- - LiteSATA: a small footprint and configurable SATA core
MiSoC comes with built-in support for the following boards:
* Mixxeo, the digital video mixer from M-Labs [XC6SLX45]
+++ /dev/null
-Unless otherwise noted, LiteSATA is copyright (C) 2014-2015 The University of
-Hong Kong
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-1. Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-
-Other authors retain ownership of their contributions. If a submission can
-reasonably be considered independently copyrightable, it's yours and we
-encourage you to claim it with appropriate copyright notices. This submission
-then falls under the "otherwise noted" category. All submissions are strongly
-encouraged to use the two-clause BSD license reproduced above.
+++ /dev/null
- __ _ __ _______ _________
- / / (_) /____ / __/ _ /_ __/ _ |
- / /__/ / __/ -_)\ \/ __ |/ / / __ |
- /____/_/\__/\__/___/_/ |_/_/ /_/ |_|
-
- Copyright 2014-2015 The University of Hong Kong
-
- A small footprint and configurable SATA core
- developed for HKU by M-Labs Ltd & EnjoyDigital
-
-[> Doc
----------
-HTML : www.enjoy-digital.fr/litesata/
-PDF : www.enjoy-digital.fr/litesata.pdf
-
-[> Intro
----------
-LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
-
-LiteSATA is part of MiSoC libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of
-components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
-
-The core uses simple and specific streaming buses and will provides in the future
-adapters to use standardized AXI or Avalon-ST streaming buses.
-
-Since Python is used to describe the HDL, the core is highly and easily
-configurable.
-
-The synthetizable BIST can be used as a starting point to integrate SATA in
-your own SoC.
-
-LiteSATA uses technologies developed in partnership with M-Labs Ltd:
- - Migen enables generating HDL with Python in an efficient way.
- - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
-
-LiteSATA can be used as MiSoC library or can be integrated with your standard
-design flow by generating the verilog rtl that you will use as a standard core.
-
-[> Features
------------
-PHY:
- - OOB, COMWAKE, COMINIT
- - ALIGN inserter/remover and bytes alignment on K28.5
- - 8B/10B encoding/decoding in transceiver
- - Errors detection and reporting
- - 32 bits interface
- - 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)
-Core:
- Link:
- - CONT inserter/remover
- - Scrambling/Descrambling of data
- - CRC inserter/checker
- - HOLD insertion/detection
- - Errors detection and reporting
- Transport/Command:
- - Easy to use user interfaces (Can be used with or without CPU)
- - 48 bits sector addressing
- - 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE
- - Errors detection and reporting
-
-Frontend:
- - Configurable crossbar (simply declare your crossbar and use crossbar.get_port() to add a new port!)
- - Ports arbitration transparent to the user
- - Synthetizable BIST
- - Striping module to segment data on multiple HDDs and increase write/read speed and capacity. (RAID0 equivalent)
- - Mirroring module for data redundancy and increase read speeds. (RAID1 equivalent)
-
-[> Possibles improvements
--------------------------
-- add standardized interfaces (AXI, Avalon-ST)
-- add NCQ support
-- add AES hardware encryption
-- add on-the-flow compression/decompression
-- add support for Altera PHYs.
-- add support for Lattice PHYs.
-- add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are
- supported)
-- add Zynq Linux drivers.
-- ... See below Support and consulting :)
-
-If you want to support these features, please contact us at florent [AT]
-enjoy-digital.fr. You can also contact our partner on the public mailing list
-devel [AT] lists.m-labs.hk.
-
-
-[> Getting started
-------------------
-1. Install Python3 and your vendor's software
-
-2. Obtain Migen and install it:
- git clone https://github.com/m-labs/migen
- cd migen
- python3 setup.py install
- cd ..
-
-3. Obtain MiSoC and install it:
- git clone https://github.com/m-labs/misoc --recursive
- cd misoc
- python3 setup.pu install
- cd ..
-
-5. Build and load BIST design (only for KC705 for now):
- go to ./example_designs/
- run ./make.py all
-
-6. Test design (only for KC705 for now):
- go to ./example_designs/test/
- run ./bist.py --port <your_serial_port>
-
-7. If you only want to build the core and use it with your
- regular design flow:
- go to ./litesata/example_designs/
- run ./make.py -t core build-core
- You can customize the core in ./example_designs/targets/core.py
-
-[> Simulations:
- Simulations are available in ./test:
- - crc_tb
- - scrambler_tb
- - phy_datapath_tb
- - link_tb
- - command_tb
- - bist_tb
- Models for all the layers of SATA and a simplified HDD model are
- provided.
- To run a simulation, go to ./test and run:
- make <simulation_name>
-
-[> Tests :
- A synthetizable BIST is provided and can be controlled with ./test/bist.py
- By using LiteScope and the provided ./test/test_link.py example you are able to
- visualize the internal logic of the design and even inject the captured data in
- the HDD model!
-
-[> License
------------
-LiteSATA is released under the very permissive two-clause BSD license. Under the
-terms of this license, you are authorized to use LiteSATA for closed-source
-proprietary designs.
-Even though we do not require you to do so, those things are awesome, so please
-do them if possible:
- - tell us that you are using LiteSATA
- - cite LiteSATA in publications related to research it has helped
- - send us feedback and suggestions for improvements
- - send us bug reports when something goes wrong
- - send us the modifications and improvements you have done to LiteSATA.
-
-[> Support and consulting
---------------------------
-We love open-source hardware and like sharing our designs with others.
-
-LiteSATA is mainly developed and maintained by EnjoyDigital.
-
-If you would like to know more about LiteSATA or if you are already a happy user
-and would like to extend it for your needs, EnjoyDigital can provide standard
-commercial support as well as consulting services.
-
-So feel free to contact us, we'd love to work with you! (and eventually shorten
-the list of the possible improvements :)
-
-[> Contact
-E-mail: florent [AT] enjoy-digital.fr
+++ /dev/null
-import math
-
-from migen.fhdl.std import *
-from migen.fhdl.decorators import ModuleTransformer
-from migen.genlib.resetsync import *
-from migen.genlib.fsm import *
-from migen.genlib.record import *
-from migen.genlib.misc import chooser, optree, Counter, WaitTimer
-from migen.genlib.cdc import *
-from migen.flow.actor import *
-from migen.flow.plumbing import Multiplexer, Demultiplexer
-from migen.actorlib.fifo import *
-from migen.actorlib.structuring import Pipeline, Converter
-from migen.actorlib.packet import Buffer
-from migen.actorlib.misc import BufferizeEndpoints
-from migen.actorlib.packet import HeaderField, Header
-
-bitrates = {
- "sata_gen3": 6.0,
- "sata_gen2": 3.0,
- "sata_gen1": 1.5,
-}
-
-frequencies = {
- "sata_gen3": 150.0,
- "sata_gen2": 75.0,
- "sata_gen1": 37.5,
-}
-
-# PHY / Link Layers
-primitives = {
- "ALIGN": 0x7B4A4ABC,
- "CONT": 0X9999AA7C,
- "SYNC": 0xB5B5957C,
- "R_RDY": 0x4A4A957C,
- "R_OK": 0x3535B57C,
- "R_ERR": 0x5656B57C,
- "R_IP": 0X5555B57C,
- "X_RDY": 0x5757B57C,
- "CONT": 0x9999AA7C,
- "WTRM": 0x5858B57C,
- "SOF": 0x3737B57C,
- "EOF": 0xD5D5B57C,
- "HOLD": 0xD5D5AA7C,
- "HOLDA": 0X9595AA7C
-}
-
-
-def is_primitive(dword):
- for k, v in primitives.items():
- if dword == v:
- return True
- return False
-
-
-def decode_primitive(dword):
- for k, v in primitives.items():
- if dword == v:
- return k
- return ""
-
-
-def phy_description(dw):
- layout = [
- ("data", dw),
- ("charisk", dw//8),
- ]
- return EndpointDescription(layout, packetized=False)
-
-
-def link_description(dw):
- layout = [
- ("d", dw),
- ("error", 1)
- ]
- return EndpointDescription(layout, packetized=True)
-
-# Transport Layer
-fis_max_dwords = 2048
-
-fis_types = {
- "REG_H2D": 0x27,
- "REG_D2H": 0x34,
- "DMA_ACTIVATE_D2H": 0x39,
- "PIO_SETUP_D2H": 0x5F,
- "DATA": 0x46
-}
-
-fis_reg_h2d_header_length = 5
-fis_reg_h2d_header_fields = {
- "type": HeaderField(0*4, 0, 8),
- "pm_port": HeaderField(0*4, 8, 4),
- "c": HeaderField(0*4, 15, 1),
- "command": HeaderField(0*4, 16, 8),
- "features_lsb": HeaderField(0*4, 24, 8),
-
- "lba_lsb": HeaderField(1*4, 0, 24),
- "device": HeaderField(1*4, 24, 8),
-
- "lba_msb": HeaderField(2*4, 0, 24),
- "features_msb": HeaderField(2*4, 24, 8),
-
- "count": HeaderField(3*4, 0, 16),
- "icc": HeaderField(3*4, 16, 8),
- "control": HeaderField(3*4, 24, 8)
-}
-fis_reg_h2d_header = Header(fis_reg_h2d_header_fields,
- fis_reg_h2d_header_length,
- swap_field_bytes=False)
-
-fis_reg_d2h_header_length = 5
-fis_reg_d2h_header_fields = {
- "type": HeaderField(0*4, 0, 8),
- "pm_port": HeaderField(0*4, 8, 4),
- "i": HeaderField(0*4, 14, 1),
- "status": HeaderField(0*4, 16, 8),
- "error": HeaderField(0*4, 24, 8),
-
- "lba_lsb": HeaderField(1*4, 0, 24),
- "device": HeaderField(1*4, 24, 8),
-
- "lba_msb": HeaderField(2*4, 0, 24),
-
- "count": HeaderField(3*4, 0, 16)
-}
-fis_reg_d2h_header = Header(fis_reg_d2h_header_fields,
- fis_reg_d2h_header_length,
- swap_field_bytes=False)
-
-fis_dma_activate_d2h_header_length = 1
-fis_dma_activate_d2h_header_fields = {
- "type": HeaderField(0*4, 0, 8),
- "pm_port": HeaderField(0*4, 8, 4)
-}
-fis_dma_activate_d2h_header = Header(fis_dma_activate_d2h_header_fields,
- fis_dma_activate_d2h_header_length,
- swap_field_bytes=False)
-
-fis_pio_setup_d2h_header_length = 5
-fis_pio_setup_d2h_header_fields = {
- "type": HeaderField(0*4, 0, 8),
- "pm_port": HeaderField(0*4, 8, 4),
- "d": HeaderField(0*4, 13, 1),
- "i": HeaderField(0*4, 14, 1),
- "status": HeaderField(0*4, 16, 8),
- "error": HeaderField(0*4, 24, 8),
-
- "lba_lsb": HeaderField(1*4, 0, 24),
-
- "lba_msb": HeaderField(2*4, 0, 24),
-
- "count": HeaderField(3*4, 0, 16),
-
- "transfer_count": HeaderField(4*4, 0, 16),
-}
-fis_pio_setup_d2h_header = Header(fis_pio_setup_d2h_header_fields,
- fis_pio_setup_d2h_header_length,
- swap_field_bytes=False)
-
-fis_data_header_length = 1
-fis_data_header_fields = {
- "type": HeaderField(0, 0, 8)
-}
-fis_data_header = Header(fis_data_header_fields,
- fis_data_header_length,
- swap_field_bytes=False)
-
-
-def transport_tx_description(dw):
- layout = [
- ("type", 8),
- ("pm_port", 4),
- ("c", 1),
- ("command", 8),
- ("features", 16),
- ("lba", 48),
- ("device", 8),
- ("count", 16),
- ("icc", 8),
- ("control", 8),
- ("data", dw)
- ]
- return EndpointDescription(layout, packetized=True)
-
-
-def transport_rx_description(dw):
- layout = [
- ("type", 8),
- ("pm_port", 4),
- ("r", 1),
- ("d", 1),
- ("i", 1),
- ("status", 8),
- ("errors", 8),
- ("lba", 48),
- ("device", 8),
- ("count", 16),
- ("transfer_count", 16),
- ("data", dw),
- ("error", 1)
- ]
- return EndpointDescription(layout, packetized=True)
-
-# Command Layer
-regs = {
- "WRITE_DMA_EXT": 0x35,
- "READ_DMA_EXT": 0x25,
- "IDENTIFY_DEVICE": 0xEC
-}
-
-reg_d2h_status = {
- "bsy": 7,
- "drdy": 6,
- "df": 5,
- "se": 5,
- "dwe": 4,
- "drq": 3,
- "ae": 2,
- "sns": 1,
- "cc": 0,
- "err": 0
-}
-
-
-def command_tx_description(dw):
- layout = [
- ("write", 1),
- ("read", 1),
- ("identify", 1),
- ("sector", 48),
- ("count", 16),
- ("data", dw)
- ]
- return EndpointDescription(layout, packetized=True)
-
-
-def command_rx_description(dw):
- layout = [
- ("write", 1),
- ("read", 1),
- ("identify", 1),
- ("last", 1),
- ("failed", 1),
- ("data", dw)
- ]
- return EndpointDescription(layout, packetized=True)
-
-
-def command_rx_cmd_description(dw):
- layout = [
- ("write", 1),
- ("read", 1),
- ("identify", 1),
- ("last", 1),
- ("failed", 1)
- ]
- return EndpointDescription(layout, packetized=False)
-
-
-def command_rx_data_description(dw):
- layout = [
- ("data", dw)
- ]
- return EndpointDescription(layout, packetized=True)
-
-# HDD
-logical_sector_size = 512 # constant since all HDDs use this
-
-
-def dwords2sectors(n):
- return math.ceil(n*4/logical_sector_size)
-
-
-def sectors2dwords(n):
- return n*logical_sector_size//4
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.core.link import LiteSATALink
-from misoclib.mem.litesata.core.transport import LiteSATATransport
-from misoclib.mem.litesata.core.command import LiteSATACommand
-
-
-class LiteSATACore(Module):
- def __init__(self, phy, buffer_depth=2*fis_max_dwords):
- self.submodules.link = LiteSATALink(phy, buffer_depth)
- self.submodules.transport = LiteSATATransport(self.link)
- self.submodules.command = LiteSATACommand(self.transport)
- self.sink, self.source = self.command.sink, self.command.source
+++ /dev/null
-from misoclib.mem.litesata.common import *
-
-tx_to_rx = [
- ("write", 1),
- ("read", 1),
- ("identify", 1),
- ("count", 16)
-]
-
-rx_to_tx = [
- ("dma_activate", 1),
- ("d2h_error", 1)
-]
-
-
-class LiteSATACommandTX(Module):
- def __init__(self, transport):
- self.sink = sink = Sink(command_tx_description(32))
- self.to_rx = to_rx = Source(tx_to_rx)
- self.from_rx = from_rx = Sink(rx_to_tx)
-
- # # #
-
- self.comb += [
- transport.sink.pm_port.eq(0),
- transport.sink.features.eq(0),
- transport.sink.lba.eq(sink.sector),
- transport.sink.device.eq(0xe0),
- transport.sink.count.eq(sink.count),
- transport.sink.icc.eq(0),
- transport.sink.control.eq(0),
- transport.sink.data.eq(sink.data)
- ]
-
- dwords_counter = Counter(max=fis_max_dwords)
- self.submodules += dwords_counter
-
- is_write = Signal()
- is_read = Signal()
- is_identify = Signal()
-
- self.fsm = fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
- fsm.act("IDLE",
- sink.ack.eq(0),
- If(sink.stb & sink.sop,
- NextState("SEND_CMD")
- ).Else(
- sink.ack.eq(1)
- )
- )
- self.sync += \
- If(fsm.ongoing("IDLE"),
- is_write.eq(sink.write),
- is_read.eq(sink.read),
- is_identify.eq(sink.identify),
- )
-
- fsm.act("SEND_CMD",
- transport.sink.stb.eq(sink.stb),
- transport.sink.sop.eq(1),
- transport.sink.eop.eq(1),
- transport.sink.c.eq(1),
- If(transport.sink.stb & transport.sink.ack,
- If(is_write,
- NextState("WAIT_DMA_ACTIVATE")
- ).Else(
- sink.ack.eq(1),
- NextState("IDLE")
- )
- )
- )
- fsm.act("WAIT_DMA_ACTIVATE",
- dwords_counter.reset.eq(1),
- If(from_rx.dma_activate,
- NextState("SEND_DATA")
- ).Elif(from_rx.d2h_error,
- sink.ack.eq(1),
- NextState("IDLE")
- )
- )
- fsm.act("SEND_DATA",
- dwords_counter.ce.eq(sink.stb & sink.ack),
-
- transport.sink.stb.eq(sink.stb),
- transport.sink.sop.eq(dwords_counter.value == 0),
- transport.sink.eop.eq((dwords_counter.value == (fis_max_dwords-1)) |
- sink.eop),
-
- sink.ack.eq(transport.sink.ack),
- If(sink.stb & sink.ack,
- If(sink.eop,
- NextState("IDLE")
- ).Elif(dwords_counter.value == (fis_max_dwords-1),
- NextState("WAIT_DMA_ACTIVATE")
- )
- )
- )
- self.comb += \
- If(fsm.ongoing("SEND_DATA"),
- transport.sink.type.eq(fis_types["DATA"]),
- ).Else(
- transport.sink.type.eq(fis_types["REG_H2D"]),
- If(is_write,
- transport.sink.command.eq(regs["WRITE_DMA_EXT"])
- ).Elif(is_read,
- transport.sink.command.eq(regs["READ_DMA_EXT"]),
- ).Else(
- transport.sink.command.eq(regs["IDENTIFY_DEVICE"]),
- )
- )
- self.comb += [
- If(sink.stb,
- to_rx.write.eq(sink.write),
- to_rx.read.eq(sink.read),
- to_rx.identify.eq(sink.identify),
- to_rx.count.eq(sink.count)
- )
- ]
-
-
-class LiteSATACommandRX(Module):
- def __init__(self, transport):
- self.source = source = Source(command_rx_description(32))
- self.to_tx = to_tx = Source(rx_to_tx)
- self.from_tx = from_tx = Sink(tx_to_rx)
-
- # # #
-
- def test_type(name):
- return transport.source.type == fis_types[name]
-
- is_identify = Signal()
- is_dma_activate = Signal()
- read_ndwords = Signal(max=sectors2dwords(2**16))
- dwords_counter = Counter(max=sectors2dwords(2**16))
- self.submodules += dwords_counter
- read_done = Signal()
-
- self.sync += \
- If(from_tx.read,
- read_ndwords.eq(from_tx.count*sectors2dwords(1)-1)
- )
- self.comb += read_done.eq(dwords_counter.value == read_ndwords)
-
- d2h_error = Signal()
- clr_d2h_error = Signal()
- set_d2h_error = Signal()
- self.sync += \
- If(clr_d2h_error,
- d2h_error.eq(0)
- ).Elif(set_d2h_error,
- d2h_error.eq(1)
- )
-
- read_error = Signal()
- clr_read_error = Signal()
- set_read_error = Signal()
- self.sync += \
- If(clr_read_error,
- read_error.eq(0)
- ).Elif(set_read_error,
- read_error.eq(1)
- )
-
- self.fsm = fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
- fsm.act("IDLE",
- dwords_counter.reset.eq(1),
- transport.source.ack.eq(1),
- clr_d2h_error.eq(1),
- clr_read_error.eq(1),
- If(from_tx.write,
- NextState("WAIT_WRITE_ACTIVATE_OR_REG_D2H")
- ).Elif(from_tx.read,
- NextState("WAIT_READ_DATA_OR_REG_D2H"),
- ).Elif(from_tx.identify,
- NextState("WAIT_PIO_SETUP_D2H"),
- )
- )
- self.sync += \
- If(fsm.ongoing("IDLE"),
- is_identify.eq(from_tx.identify)
- )
- fsm.act("WAIT_WRITE_ACTIVATE_OR_REG_D2H",
- transport.source.ack.eq(1),
- If(transport.source.stb,
- If(test_type("DMA_ACTIVATE_D2H"),
- is_dma_activate.eq(1),
- ).Elif(test_type("REG_D2H"),
- set_d2h_error.eq(transport.source.status[reg_d2h_status["err"]]),
- NextState("PRESENT_WRITE_RESPONSE")
- )
- )
- )
- fsm.act("PRESENT_WRITE_RESPONSE",
- source.stb.eq(1),
- source.sop.eq(1),
- source.eop.eq(1),
- source.write.eq(1),
- source.last.eq(1),
- source.failed.eq(transport.source.error | d2h_error),
- If(source.stb & source.ack,
- NextState("IDLE")
- )
- )
- fsm.act("WAIT_READ_DATA_OR_REG_D2H",
- transport.source.ack.eq(1),
- If(transport.source.stb,
- transport.source.ack.eq(0),
- If(test_type("DATA"),
- NextState("PRESENT_READ_DATA")
- ).Elif(test_type("REG_D2H"),
- NextState("PRESENT_READ_RESPONSE")
- )
- )
- )
- fsm.act("WAIT_PIO_SETUP_D2H",
- transport.source.ack.eq(1),
- If(transport.source.stb,
- transport.source.ack.eq(0),
- If(test_type("PIO_SETUP_D2H"),
- NextState("PRESENT_PIO_SETUP_D2H")
- )
- )
- )
- fsm.act("PRESENT_PIO_SETUP_D2H",
- transport.source.ack.eq(1),
- If(transport.source.stb & transport.source.eop,
- NextState("WAIT_READ_DATA_OR_REG_D2H")
- )
- )
-
- fsm.act("PRESENT_READ_DATA",
- set_read_error.eq(transport.source.error),
- source.stb.eq(transport.source.stb),
- source.sop.eq(transport.source.sop),
- source.eop.eq(transport.source.eop),
- source.read.eq(~is_identify),
- source.identify.eq(is_identify),
- source.failed.eq(transport.source.error),
- source.last.eq(is_identify),
- source.data.eq(transport.source.data),
- transport.source.ack.eq(source.ack),
- If(source.stb & source.ack,
- dwords_counter.ce.eq(~read_done),
- If(source.eop,
- If(is_identify,
- NextState("IDLE")
- ).Else(
- NextState("WAIT_READ_DATA_OR_REG_D2H")
- )
- )
- )
- )
-
- fsm.act("PRESENT_READ_RESPONSE",
- source.stb.eq(1),
- source.sop.eq(1),
- source.eop.eq(1),
- source.read.eq(1),
- source.last.eq(1),
- source.failed.eq(~read_done | read_error | d2h_error),
- If(source.stb & source.ack,
- NextState("IDLE")
- )
- )
-
- self.comb += [
- to_tx.dma_activate.eq(is_dma_activate),
- to_tx.d2h_error.eq(d2h_error)
- ]
-
-
-class LiteSATACommand(Module):
- def __init__(self, transport):
- self.submodules.tx = LiteSATACommandTX(transport)
- self.submodules.rx = LiteSATACommandRX(transport)
- self.comb += [
- self.rx.to_tx.connect(self.tx.from_rx),
- self.tx.to_rx.connect(self.rx.from_tx)
- ]
- self.sink, self.source = self.tx.sink, self.rx.source
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.core.link.crc import LiteSATACRCInserter, LiteSATACRCChecker
-from misoclib.mem.litesata.core.link.scrambler import LiteSATAScrambler
-from misoclib.mem.litesata.core.link.cont import LiteSATACONTInserter, LiteSATACONTRemover
-
-from_rx = [
- ("idle", 1),
- ("insert", 32),
- ("det", 32)
-]
-
-
-class LiteSATALinkTX(Module):
- def __init__(self, phy):
- self.sink = Sink(link_description(32))
- self.from_rx = Sink(from_rx)
-
- # # #
-
- self.fsm = fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
-
- # insert CRC
- crc = LiteSATACRCInserter(link_description(32))
- self.submodules += crc
-
- # scramble
- scrambler = LiteSATAScrambler(link_description(32))
- self.submodules += scrambler
-
- # connect CRC / scrambler
- self.comb += [
- Record.connect(self.sink, crc.sink),
- Record.connect(crc.source, scrambler.sink)
- ]
-
- # inserter CONT and scrambled data between
- # CONT and next primitive
- cont = BufferizeEndpoints("sink")(LiteSATACONTInserter(phy_description(32)))
- self.submodules += cont
-
- # datas / primitives mux
- insert = Signal(32)
- copy = Signal()
- self.comb += [
- If(self.from_rx.insert,
- cont.sink.stb.eq(1),
- cont.sink.data.eq(self.from_rx.insert),
- cont.sink.charisk.eq(0x0001),
- ).
- Elif(insert,
- cont.sink.stb.eq(1),
- cont.sink.data.eq(insert),
- cont.sink.charisk.eq(0x0001),
- ).Elif(copy,
- cont.sink.stb.eq(scrambler.source.stb),
- cont.sink.data.eq(scrambler.source.d),
- scrambler.source.ack.eq(cont.sink.ack),
- cont.sink.charisk.eq(0)
- )
- ]
- self.comb += Record.connect(cont.source, phy.sink)
-
- # FSM
- fsm.act("IDLE",
- scrambler.reset.eq(1),
- If(self.from_rx.idle,
- insert.eq(primitives["SYNC"]),
- If(scrambler.source.stb & scrambler.source.sop,
- If(self.from_rx.det == primitives["SYNC"],
- NextState("RDY")
- )
- )
- )
- )
- fsm.act("RDY",
- insert.eq(primitives["X_RDY"]),
- If(~self.from_rx.idle,
- NextState("IDLE")
- ).Elif(self.from_rx.det == primitives["R_RDY"],
- NextState("SOF")
- )
- )
- fsm.act("SOF",
- insert.eq(primitives["SOF"]),
- If(phy.sink.ack,
- NextState("COPY")
- )
- )
- fsm.act("COPY",
- copy.eq(1),
- If(self.from_rx.det == primitives["HOLD"],
- insert.eq(primitives["HOLDA"]),
- ).Elif(~scrambler.source.stb,
- insert.eq(primitives["HOLD"]),
- ).Elif(scrambler.source.stb &
- scrambler.source.eop &
- scrambler.source.ack,
- NextState("EOF")
- )
- )
- fsm.act("EOF",
- insert.eq(primitives["EOF"]),
- If(phy.sink.ack,
- NextState("WTRM")
- )
- )
- fsm.act("WTRM",
- insert.eq(primitives["WTRM"]),
- If(self.from_rx.det == primitives["R_OK"],
- NextState("IDLE")
- ).Elif(self.from_rx.det == primitives["R_ERR"],
- NextState("IDLE")
- )
- )
-
-
-class LiteSATALinkRX(Module):
- def __init__(self, phy):
- self.source = Source(link_description(32))
- self.hold = Signal()
- self.to_tx = Source(from_rx)
-
- # # #
-
- self.fsm = fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
-
- # CONT remover
- cont = BufferizeEndpoints("source")(LiteSATACONTRemover(phy_description(32)))
- self.submodules += cont
- self.comb += Record.connect(phy.source, cont.sink)
-
- # datas / primitives detection
- insert = Signal(32)
- det = Signal(32)
- self.comb += \
- If(cont.source.stb & (cont.source.charisk == 0b0001),
- det.eq(cont.source.data)
- )
-
- # descrambler
- scrambler = LiteSATAScrambler(link_description(32))
- self.submodules += scrambler
-
- # check CRC
- crc = LiteSATACRCChecker(link_description(32))
- self.submodules += crc
-
- idle = Signal()
- copy = Signal()
-
- sop = Signal()
- eop = Signal()
- self.sync += \
- If(idle,
- sop.eq(1),
- ).Elif(copy,
- If(scrambler.sink.stb & scrambler.sink.ack,
- sop.eq(0)
- )
- )
- self.comb += eop.eq(det == primitives["EOF"])
-
- crc_error = Signal()
- self.sync += \
- If(crc.source.stb & crc.source.eop & crc.source.ack,
- crc_error.eq(crc.source.error)
- )
-
- # graph
- self.comb += [
- cont.source.ack.eq(1),
- Record.connect(scrambler.source, crc.sink),
- Record.connect(crc.source, self.source),
- ]
- cont_source_data_d = Signal(32)
- self.sync += \
- If(cont.source.stb & (det == 0),
- scrambler.sink.d.eq(cont.source.data)
- )
-
- # FSM
- fsm.act("IDLE",
- idle.eq(1),
- scrambler.reset.eq(1),
- If(det == primitives["X_RDY"],
- NextState("RDY")
- )
- )
- fsm.act("RDY",
- insert.eq(primitives["R_RDY"]),
- If(det == primitives["SOF"],
- NextState("WAIT_FIRST")
- )
- )
- fsm.act("WAIT_FIRST",
- insert.eq(primitives["R_IP"]),
- If(cont.source.stb & (det == 0),
- NextState("COPY")
- )
- )
- self.comb += [
- scrambler.sink.sop.eq(sop),
- scrambler.sink.eop.eq(eop)
- ]
- fsm.act("COPY",
- copy.eq(1),
- scrambler.sink.stb.eq(cont.source.stb & ((det == 0) | eop)),
- insert.eq(primitives["R_IP"]),
- If(det == primitives["HOLD"],
- insert.eq(primitives["HOLDA"])
- ).Elif(det == primitives["EOF"],
- NextState("WTRM")
- ).Elif(self.hold,
- insert.eq(primitives["HOLD"])
- )
- )
- fsm.act("EOF",
- insert.eq(primitives["R_IP"]),
- If(det == primitives["WTRM"],
- NextState("WTRM")
- )
- )
- fsm.act("WTRM",
- insert.eq(primitives["R_IP"]),
- If(~crc_error,
- NextState("R_OK")
- ).Else(
- NextState("R_ERR")
- )
- )
- fsm.act("R_OK",
- insert.eq(primitives["R_OK"]),
- If(det == primitives["SYNC"],
- NextState("IDLE")
- )
- )
- fsm.act("R_ERR",
- insert.eq(primitives["R_ERR"]),
- If(det == primitives["SYNC"],
- NextState("IDLE")
- )
- )
-
- # to TX
- self.comb += [
- self.to_tx.idle.eq(fsm.ongoing("IDLE")),
- self.to_tx.insert.eq(insert),
- self.to_tx.det.eq(det)
- ]
-
-
-class LiteSATALink(Module):
- def __init__(self, phy, buffer_depth):
- self.submodules.tx_buffer = Buffer(link_description(32), buffer_depth)
- self.submodules.tx = LiteSATALinkTX(phy)
- self.submodules.rx = LiteSATALinkRX(phy)
- self.submodules.rx_buffer = Buffer(link_description(32), buffer_depth,
- almost_full=3*buffer_depth//4)
- self.comb += [
- Record.connect(self.tx_buffer.source, self.tx.sink),
- Record.connect(self.rx.to_tx, self.tx.from_rx),
- Record.connect(self.rx.source, self.rx_buffer.sink),
- self.rx.hold.eq(self.rx_buffer.almost_full)
- ]
- self.sink, self.source = self.tx_buffer.sink, self.rx_buffer.source
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.core.link.scrambler import Scrambler
-
-
-class LiteSATACONTInserter(Module):
- def __init__(self, description):
- self.sink = sink = Sink(description)
- self.source = source = Source(description)
-
- # # #
-
- counter = Counter(max=4)
- self.submodules += counter
-
- is_data = Signal()
- was_data = Signal()
- was_hold = Signal()
- change = Signal()
- self.comb += is_data.eq(sink.charisk == 0)
-
- last_data = Signal(32)
- last_primitive = Signal(32)
- last_charisk = Signal(4)
- self.sync += [
- If(sink.stb & source.ack,
- last_data.eq(sink.data),
- last_charisk.eq(sink.charisk),
- If(~is_data,
- last_primitive.eq(sink.data),
- ),
- was_data.eq(is_data),
- was_hold.eq(last_primitive == primitives["HOLD"])
- )
- ]
- self.comb += change.eq(
- (sink.data != last_data) |
- (sink.charisk != last_charisk) |
- is_data
- )
-
- # scrambler
- scrambler = InsertReset(Scrambler())
- self.submodules += scrambler
-
- # Datapath
- self.comb += [
- Record.connect(sink, source),
- If(sink.stb,
- If(~change,
- counter.ce.eq(sink.ack & (counter.value != 2)),
- # insert CONT
- If(counter.value == 1,
- source.charisk.eq(0b0001),
- source.data.eq(primitives["CONT"])
- # insert scrambled data for EMI
- ).Elif(counter.value == 2,
- scrambler.ce.eq(sink.ack),
- source.charisk.eq(0b0000),
- source.data.eq(scrambler.value)
- )
- ).Else(
- counter.reset.eq(source.ack),
- If(counter.value == 2,
- # Reinsert last primitive
- If(is_data | (~is_data & was_hold),
- source.stb.eq(1),
- sink.ack.eq(0),
- source.charisk.eq(0b0001),
- source.data.eq(last_primitive)
- )
- )
- )
- )
- ]
-
-
-class LiteSATACONTRemover(Module):
- def __init__(self, description):
- self.sink = sink = Sink(description)
- self.source = source = Source(description)
-
- # # #
-
- is_data = Signal()
- is_cont = Signal()
- in_cont = Signal()
- cont_ongoing = Signal()
-
- self.comb += [
- is_data.eq(sink.charisk == 0),
- is_cont.eq(~is_data & (sink.data == primitives["CONT"]))
- ]
- self.sync += \
- If(sink.stb & sink.ack,
- If(is_cont,
- in_cont.eq(1)
- ).Elif(~is_data,
- in_cont.eq(0)
- )
- )
- self.comb += cont_ongoing.eq(is_cont | (in_cont & is_data))
-
- # Datapath
- last_primitive = Signal(32)
- self.sync += [
- If(sink.stb & sink.ack,
- If(~is_data & ~is_cont,
- last_primitive.eq(sink.data)
- )
- )
- ]
- self.comb += [
- Record.connect(sink, source),
- If(cont_ongoing,
- source.charisk.eq(0b0001),
- source.data.eq(last_primitive)
- )
- ]
+++ /dev/null
-from collections import OrderedDict
-from misoclib.mem.litesata.common import *
-
-
-class CRCEngine(Module):
- """Cyclic Redundancy Check Engine
-
- Compute next CRC value from last CRC value and data input using
- an optimized asynchronous LFSR.
-
- Parameters
- ----------
- width : int
- Width of the data bus and CRC.
- polynom : int
- Polynom of the CRC (ex: 0x04C11DB7 for IEEE 802.3 CRC)
-
- Attributes
- ----------
- d : in
- Data input.
- last : in
- last CRC value.
- next :
- next CRC value.
- """
- def __init__(self, width, polynom):
- self.d = Signal(width)
- self.last = Signal(width)
- self.next = Signal(width)
-
- # # #
-
- def _optimize_eq(l):
- """
- Replace even numbers of XORs in the equation
- with an equivalent XOR
- """
- d = OrderedDict()
- for e in l:
- if e in d:
- d[e] += 1
- else:
- d[e] = 1
- r = []
- for key, value in d.items():
- if value%2 != 0:
- r.append(key)
- return r
-
- new = Signal(32)
- self.comb += new.eq(self.last ^ self.d)
-
- # compute and optimize CRC's LFSR
- curval = [[("new", i)] for i in range(width)]
- for i in range(width):
- feedback = curval.pop()
- for j in range(width-1):
- if (polynom & (1<<(j+1))):
- curval[j] += feedback
- curval[j] = _optimize_eq(curval[j])
- curval.insert(0, feedback)
-
- # implement logic
- for i in range(width):
- xors = []
- for t, n in curval[i]:
- if t == "new":
- xors += [new[n]]
- self.comb += self.next[i].eq(optree("^", xors))
-
-
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class LiteSATACRC(Module):
- """SATA CRC
-
- Implement a SATA CRC generator/checker
-
- Attributes
- ----------
- value : out
- CRC value (used for generator).
- error : out
- CRC error (used for checker).
- """
- width = 32
- polynom = 0x04C11DB7
- init = 0x52325032
- check = 0x00000000
-
- def __init__(self, dw=32):
- self.d = Signal(self.width)
- self.value = Signal(self.width)
- self.error = Signal()
-
- # # #
-
- engine = CRCEngine(self.width, self.polynom)
- self.submodules += engine
- reg_i = Signal(self.width, reset=self.init)
- self.sync += reg_i.eq(engine.next)
- self.comb += [
- engine.d.eq(self.d),
- engine.last.eq(reg_i),
-
- self.value.eq(reg_i),
- self.error.eq(engine.next != self.check)
- ]
-
-
-class CRCInserter(Module):
- """CRC Inserter
-
- Append a CRC at the end of each packet.
-
- Parameters
- ----------
- layout : layout
- Layout of the dataflow.
-
- Attributes
- ----------
- sink : in
- Packets input without CRC.
- source : out
- Packets output with CRC.
- """
- def __init__(self, crc_class, layout):
- self.sink = sink = Sink(layout)
- self.source = source = Source(layout)
- self.busy = Signal()
-
- # # #
-
- dw = flen(sink.d)
- crc = crc_class(dw)
- fsm = FSM(reset_state="IDLE")
- self.submodules += crc, fsm
-
- fsm.act("IDLE",
- crc.reset.eq(1),
- sink.ack.eq(1),
- If(sink.stb & sink.sop,
- sink.ack.eq(0),
- NextState("COPY"),
- )
- )
- fsm.act("COPY",
- crc.ce.eq(sink.stb & source.ack),
- crc.d.eq(sink.d),
- Record.connect(sink, source),
- source.eop.eq(0),
- If(sink.stb & sink.eop & source.ack,
- NextState("INSERT"),
- )
- )
- ratio = crc.width//dw
- if ratio > 1:
- cnt = Signal(max=ratio, reset=ratio-1)
- cnt_done = Signal()
- fsm.act("INSERT",
- source.stb.eq(1),
- chooser(crc.value, cnt, source.d, reverse=True),
- If(cnt_done,
- source.eop.eq(1),
- If(source.ack, NextState("IDLE"))
- )
- )
- self.comb += cnt_done.eq(cnt == 0)
- self.sync += \
- If(fsm.ongoing("IDLE"),
- cnt.eq(cnt.reset)
- ).Elif(fsm.ongoing("INSERT") & ~cnt_done,
- cnt.eq(cnt - source.ack)
- )
- else:
- fsm.act("INSERT",
- source.stb.eq(1),
- source.eop.eq(1),
- source.d.eq(crc.value),
- If(source.ack, NextState("IDLE"))
- )
- self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
-
-
-class CRCChecker(Module):
- """CRC Checker
-
- Check CRC at the end of each packet.
-
- Parameters
- ----------
- layout : layout
- Layout of the dataflow.
-
- Attributes
- ----------
- sink : in
- Packets input with CRC.
- source : out
- Packets output without CRC and "error" set to 0
- on eop when CRC OK / set to 1 when CRC KO.
- """
- def __init__(self, crc_class, layout):
- self.sink = sink = Sink(layout)
- self.source = source = Source(layout)
- self.busy = Signal()
-
- # # #
-
- dw = flen(sink.d)
- crc = crc_class(dw)
- self.submodules += crc
- ratio = crc.width//dw
-
- error = Signal()
- fifo = InsertReset(SyncFIFO(layout, ratio + 1))
- self.submodules += fifo
-
- fsm = FSM(reset_state="RESET")
- self.submodules += fsm
-
- fifo_in = Signal()
- fifo_out = Signal()
- fifo_full = Signal()
-
- self.comb += [
- fifo_full.eq(fifo.fifo.level == ratio),
- fifo_in.eq(sink.stb & (~fifo_full | fifo_out)),
- fifo_out.eq(source.stb & source.ack),
-
- Record.connect(sink, fifo.sink),
- fifo.sink.stb.eq(fifo_in),
- self.sink.ack.eq(fifo_in),
-
- source.stb.eq(sink.stb & fifo_full),
- source.sop.eq(fifo.source.sop),
- source.eop.eq(sink.eop),
- fifo.source.ack.eq(fifo_out),
- source.payload.eq(fifo.source.payload),
-
- source.error.eq(sink.error | crc.error),
- ]
-
- fsm.act("RESET",
- crc.reset.eq(1),
- fifo.reset.eq(1),
- NextState("IDLE"),
- )
- fsm.act("IDLE",
- crc.d.eq(sink.d),
- If(sink.stb & sink.sop & sink.ack,
- crc.ce.eq(1),
- NextState("COPY")
- )
- )
- fsm.act("COPY",
- crc.d.eq(sink.d),
- If(sink.stb & sink.ack,
- crc.ce.eq(1),
- If(sink.eop,
- NextState("RESET")
- )
- )
- )
- self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
-
-
-class LiteSATACRCInserter(CRCInserter):
- def __init__(self, description):
- CRCInserter.__init__(self, LiteSATACRC, description)
-
-
-class LiteSATACRCChecker(CRCChecker):
- def __init__(self, description):
- CRCChecker.__init__(self, LiteSATACRC, description)
+++ /dev/null
-from misoclib.mem.litesata.common import *
-
-
-@DecorateModule(InsertCE)
-class Scrambler(Module):
- """SATA Scrambler
-
- Implement a SATA Scrambler
-
- Attributes
- ----------
- value : out
- Scrambled value.
- """
- def __init__(self):
- self.value = Signal(32)
-
- # # #
-
- context = Signal(16, reset=0xf0f6)
- next_value = Signal(32)
- self.sync += context.eq(next_value[16:32])
-
- # XXX: from SATA specification, replace it with
- # a generic implementation using polynoms.
- lfsr_coefs = (
- (15, 13, 4, 0), # 0
- (15, 14, 13, 5, 4, 1, 0),
- (14, 13, 6, 5, 4, 2, 1, 0),
- (15, 14, 7, 6, 5, 3, 2, 1),
- (13, 8, 7, 6, 3, 2, 0),
- (14, 9, 8, 7, 4, 3, 1),
- (15, 10, 9, 8, 5, 4, 2),
- (15, 13, 11, 10, 9, 6, 5, 4, 3, 0),
- (15, 14, 13, 12, 11, 10, 7, 6, 5, 1, 0),
- (14, 12, 11, 8, 7, 6, 4, 2, 1, 0),
- (15, 13, 12, 9, 8, 7, 5, 3, 2, 1),
- (15, 14, 10, 9, 8, 6, 3, 2, 0),
- (13, 11, 10, 9, 7, 3, 1, 0),
- (14, 12, 11, 10, 8, 4, 2, 1),
- (15, 13, 12, 11, 9, 5, 3, 2),
- (15, 14, 12, 10, 6, 3, 0),
-
- (11, 7, 1, 0), # 16
- (12, 8, 2, 1),
- (13, 9, 3, 2),
- (14, 10, 4, 3),
- (15, 11, 5, 4),
- (15, 13, 12, 6, 5, 4, 0),
- (15, 14, 7, 6, 5, 4, 1, 0),
- (13, 8, 7, 6, 5, 4, 2, 1, 0),
- (14, 9, 8, 7, 6, 5, 3, 2, 1),
- (15, 10, 9, 8, 7, 6, 4, 3, 2),
- (15, 13, 11, 10, 9, 8, 7, 5, 3, 0),
- (15, 14, 13, 12, 11, 10, 9, 8, 6, 1, 0),
- (14, 12, 11, 10, 9, 7, 4, 2, 1, 0),
- (15, 13, 12, 11, 10, 8, 5, 3, 2, 1),
- (15, 14, 12, 11, 9, 6, 3, 2, 0),
- (12, 10, 7, 3, 1, 0),
- )
-
- for n, coefs in enumerate(lfsr_coefs):
- eq = [context[i] for i in coefs]
- self.comb += next_value[n].eq(optree("^", eq))
-
- self.comb += self.value.eq(next_value)
-
-
-@DecorateModule(InsertReset)
-class LiteSATAScrambler(Module):
- def __init__(self, description):
- self.sink = sink = Sink(description)
- self.source = source = Source(description)
-
- # # #
-
- scrambler = Scrambler()
- self.submodules += scrambler
- self.comb += [
- scrambler.ce.eq(sink.stb & sink.ack),
- Record.connect(sink, source),
- source.d.eq(sink.d ^ scrambler.value)
- ]
+++ /dev/null
-from misoclib.mem.litesata.common import *
-
-
-def test_type(name, signal):
- return signal == fis_types[name]
-
-
-class LiteSATATransportTX(Module):
- def __init__(self, link):
- self.sink = sink = Sink(transport_tx_description(32))
-
- # # #
-
- cmd_ndwords = max(fis_reg_h2d_header.length,
- fis_data_header.length)
- encoded_cmd = Signal(cmd_ndwords*32)
-
- counter = Counter(max=cmd_ndwords+1)
- self.submodules += counter
-
- cmd_len = Signal(counter.width)
- cmd_with_data = Signal()
-
- cmd_send = Signal()
- data_send = Signal()
- cmd_done = Signal()
-
- fis_type = Signal(8)
- update_fis_type = Signal()
-
- def test_type_tx(name):
- return test_type(name, sink.type)
-
- self.fsm = fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
- fsm.act("IDLE",
- sink.ack.eq(0),
- counter.reset.eq(1),
- update_fis_type.eq(1),
- If(sink.stb & sink.sop,
- If(test_type_tx("REG_H2D"),
- NextState("SEND_CTRL_CMD")
- ).Elif(test_type_tx("DATA"),
- NextState("SEND_DATA_CMD")
- ).Else(
- sink.ack.eq(1)
- )
- ).Else(
- sink.ack.eq(1)
- )
- )
- self.sync += \
- If(update_fis_type, fis_type.eq(link.source.d[:8]))
-
- fsm.act("SEND_CTRL_CMD",
- fis_reg_h2d_header.encode(sink, encoded_cmd),
- cmd_len.eq(fis_reg_h2d_header.length-1),
- cmd_send.eq(1),
- If(cmd_done,
- sink.ack.eq(1),
- NextState("IDLE")
- )
- )
- fsm.act("SEND_DATA_CMD",
- sink.ack.eq(0),
- fis_data_header.encode(sink, encoded_cmd),
- cmd_len.eq(fis_data_header.length-1),
- cmd_with_data.eq(1),
- cmd_send.eq(1),
- If(cmd_done,
- NextState("SEND_DATA")
- )
- )
- fsm.act("SEND_DATA",
- data_send.eq(1),
- sink.ack.eq(link.sink.ack),
- If(sink.stb & sink.eop & sink.ack,
- NextState("IDLE")
- )
- )
-
- cmd_cases = {}
- for i in range(cmd_ndwords):
- cmd_cases[i] = [link.sink.d.eq(encoded_cmd[32*i:32*(i+1)])]
-
- self.comb += [
- counter.ce.eq(sink.stb & link.sink.ack),
- cmd_done.eq((counter.value == cmd_len) &
- link.sink.stb &
- link.sink.ack),
- If(cmd_send,
- link.sink.stb.eq(sink.stb),
- link.sink.sop.eq(counter.value == 0),
- link.sink.eop.eq((counter.value == cmd_len) & ~cmd_with_data),
- Case(counter.value, cmd_cases)
- ).Elif(data_send,
- link.sink.stb.eq(sink.stb),
- link.sink.sop.eq(0),
- link.sink.eop.eq(sink.eop),
- link.sink.d.eq(sink.data)
- )
- ]
-
-
-class LiteSATATransportRX(Module):
- def __init__(self, link):
- self.source = source = Source(transport_rx_description(32))
-
- # # #
-
- cmd_ndwords = max(fis_reg_d2h_header.length,
- fis_dma_activate_d2h_header.length,
- fis_pio_setup_d2h_header.length,
- fis_data_header.length)
- encoded_cmd = Signal(cmd_ndwords*32)
-
- counter = Counter(max=cmd_ndwords+1)
- self.submodules += counter
-
- cmd_len = Signal(counter.width)
-
- cmd_receive = Signal()
- data_receive = Signal()
- cmd_done = Signal()
- data_done = Signal()
-
- def test_type_rx(name):
- return test_type(name, link.source.d[:8])
-
- self.fsm = fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
-
- data_sop = Signal()
- fis_type = Signal(8)
- update_fis_type = Signal()
-
- fsm.act("IDLE",
- link.source.ack.eq(0),
- counter.reset.eq(1),
- update_fis_type.eq(1),
- If(link.source.stb & link.source.sop,
- If(test_type_rx("REG_D2H"),
- NextState("RECEIVE_CTRL_CMD")
- ).Elif(test_type_rx("DMA_ACTIVATE_D2H"),
- NextState("RECEIVE_CTRL_CMD")
- ).Elif(test_type_rx("PIO_SETUP_D2H"),
- NextState("RECEIVE_CTRL_CMD")
- ).Elif(test_type_rx("DATA"),
- NextState("RECEIVE_DATA_CMD"),
- ).Else(
- link.source.ack.eq(1)
- )
- ).Else(
- link.source.ack.eq(1)
- )
- )
- self.sync += \
- If(update_fis_type, fis_type.eq(link.source.d[:8]))
-
- fsm.act("RECEIVE_CTRL_CMD",
- If(test_type("REG_D2H", fis_type),
- cmd_len.eq(fis_reg_d2h_header.length-1)
- ).Elif(test_type("DMA_ACTIVATE_D2H", fis_type),
- cmd_len.eq(fis_dma_activate_d2h_header.length-1)
- ).Else(
- cmd_len.eq(fis_pio_setup_d2h_header.length-1)
- ),
- cmd_receive.eq(1),
- link.source.ack.eq(1),
- If(cmd_done,
- NextState("PRESENT_CTRL_CMD")
- )
- )
- fsm.act("PRESENT_CTRL_CMD",
- source.stb.eq(1),
- source.sop.eq(1),
- source.eop.eq(1),
- If(test_type("REG_D2H", fis_type),
- fis_reg_d2h_header.decode(encoded_cmd, source)
- ).Elif(test_type("DMA_ACTIVATE_D2H", fis_type),
- fis_dma_activate_d2h_header.decode(encoded_cmd, source)
- ).Else(
- fis_pio_setup_d2h_header.decode(encoded_cmd, source)
- ),
- If(source.stb & source.ack,
- NextState("IDLE")
- )
- )
- fsm.act("RECEIVE_DATA_CMD",
- cmd_len.eq(fis_data_header.length-1),
- cmd_receive.eq(1),
- link.source.ack.eq(1),
- If(cmd_done,
- NextState("PRESENT_DATA")
- )
- )
- fsm.act("PRESENT_DATA",
- data_receive.eq(1),
- source.stb.eq(link.source.stb),
- fis_data_header.decode(encoded_cmd, source),
- source.sop.eq(data_sop),
- source.eop.eq(link.source.eop),
- source.error.eq(link.source.error),
- source.data.eq(link.source.d),
- link.source.ack.eq(source.ack),
- If(source.stb & source.eop & source.ack,
- NextState("IDLE")
- )
- )
-
- self.sync += \
- If(fsm.ongoing("RECEIVE_DATA_CMD"),
- data_sop.eq(1)
- ).Elif(fsm.ongoing("PRESENT_DATA"),
- If(source.stb & source.ack,
- data_sop.eq(0)
- )
- )
-
- cmd_cases = {}
- for i in range(cmd_ndwords):
- cmd_cases[i] = [encoded_cmd[32*i:32*(i+1)].eq(link.source.d)]
-
- self.comb += \
- If(cmd_receive & link.source.stb,
- counter.ce.eq(1)
- )
- self.sync += \
- If(cmd_receive,
- Case(counter.value, cmd_cases),
- )
- self.comb += cmd_done.eq((counter.value == cmd_len) & link.source.ack)
-
-
-class LiteSATATransport(Module):
- def __init__(self, link):
- self.submodules.tx = LiteSATATransportTX(link)
- self.submodules.rx = LiteSATATransportRX(link)
- self.sink, self.source = self.tx.sink, self.rx.source
+++ /dev/null
-*.diff
-*.pyc
-*~
-*.bc
-*.md
-
-# Ignore generated files
-build/
+++ /dev/null
-# Makefile for Sphinx documentation
-#
-
-# You can set these variables from the command line.
-SPHINXOPTS =
-SPHINXBUILD = sphinx-build
-PAPER =
-BUILDDIR = build
-
-# User-friendly check for sphinx-build
-ifeq ($(shell which $(SPHINXBUILD) >/dev/null 2>&1; echo $$?), 1)
-$(error The '$(SPHINXBUILD)' command was not found. Make sure you have Sphinx installed, then set the SPHINXBUILD environment variable to point to the full path of the '$(SPHINXBUILD)' executable. Alternatively you can add the directory with the executable to your PATH. If you don't have Sphinx installed, grab it from http://sphinx-doc.org/)
-endif
-
-# Internal variables.
-PAPEROPT_a4 = -D latex_paper_size=a4
-PAPEROPT_letter = -D latex_paper_size=letter
-ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) source
-# the i18n builder cannot share the environment and doctrees with the others
-I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) source
-
-.PHONY: help clean html dirhtml singlehtml pickle json htmlhelp qthelp devhelp epub latex latexpdf text man changes linkcheck doctest gettext
-
-help:
- @echo "Please use \`make <target>' where <target> is one of"
- @echo " html to make standalone HTML files"
- @echo " dirhtml to make HTML files named index.html in directories"
- @echo " singlehtml to make a single large HTML file"
- @echo " pickle to make pickle files"
- @echo " json to make JSON files"
- @echo " htmlhelp to make HTML files and a HTML help project"
- @echo " epub to make an epub"
- @echo " latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter"
- @echo " latexpdf to make LaTeX files and run them through pdflatex"
- @echo " latexpdfja to make LaTeX files and run them through platex/dvipdfmx"
- @echo " text to make text files"
- @echo " man to make manual pages"
- @echo " texinfo to make Texinfo files"
- @echo " info to make Texinfo files and run them through makeinfo"
- @echo " gettext to make PO message catalogs"
- @echo " changes to make an overview of all changed/added/deprecated items"
- @echo " xml to make Docutils-native XML files"
- @echo " pseudoxml to make pseudoxml-XML files for display purposes"
- @echo " linkcheck to check all external links for integrity"
- @echo " doctest to run all doctests embedded in the documentation (if enabled)"
-
-clean:
- rm -rf $(BUILDDIR)/*
-
-html:
- $(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
- @echo
- @echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
-
-dirhtml:
- $(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml
- @echo
- @echo "Build finished. The HTML pages are in $(BUILDDIR)/dirhtml."
-
-singlehtml:
- $(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml
- @echo
- @echo "Build finished. The HTML page is in $(BUILDDIR)/singlehtml."
-
-pickle:
- $(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle
- @echo
- @echo "Build finished; now you can process the pickle files."
-
-json:
- $(SPHINXBUILD) -b json $(ALLSPHINXOPTS) $(BUILDDIR)/json
- @echo
- @echo "Build finished; now you can process the JSON files."
-
-htmlhelp:
- $(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp
- @echo
- @echo "Build finished; now you can run HTML Help Workshop with the" \
- ".hhp project file in $(BUILDDIR)/htmlhelp."
-
-epub:
- $(SPHINXBUILD) -b epub $(ALLSPHINXOPTS) $(BUILDDIR)/epub
- @echo
- @echo "Build finished. The epub file is in $(BUILDDIR)/epub."
-
-latex:
- $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
- @echo
- @echo "Build finished; the LaTeX files are in $(BUILDDIR)/latex."
- @echo "Run \`make' in that directory to run these through (pdf)latex" \
- "(use \`make latexpdf' here to do that automatically)."
-
-latexpdf:
- $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
- @echo "Running LaTeX files through pdflatex..."
- $(MAKE) -C $(BUILDDIR)/latex all-pdf
- @echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
-
-latexpdfja:
- $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
- @echo "Running LaTeX files through platex and dvipdfmx..."
- $(MAKE) -C $(BUILDDIR)/latex all-pdf-ja
- @echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
-
-text:
- $(SPHINXBUILD) -b text $(ALLSPHINXOPTS) $(BUILDDIR)/text
- @echo
- @echo "Build finished. The text files are in $(BUILDDIR)/text."
-
-man:
- $(SPHINXBUILD) -b man $(ALLSPHINXOPTS) $(BUILDDIR)/man
- @echo
- @echo "Build finished. The manual pages are in $(BUILDDIR)/man."
-
-texinfo:
- $(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
- @echo
- @echo "Build finished. The Texinfo files are in $(BUILDDIR)/texinfo."
- @echo "Run \`make' in that directory to run these through makeinfo" \
- "(use \`make info' here to do that automatically)."
-
-info:
- $(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
- @echo "Running Texinfo files through makeinfo..."
- make -C $(BUILDDIR)/texinfo info
- @echo "makeinfo finished; the Info files are in $(BUILDDIR)/texinfo."
-
-gettext:
- $(SPHINXBUILD) -b gettext $(I18NSPHINXOPTS) $(BUILDDIR)/locale
- @echo
- @echo "Build finished. The message catalogs are in $(BUILDDIR)/locale."
-
-changes:
- $(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes
- @echo
- @echo "The overview file is in $(BUILDDIR)/changes."
-
-linkcheck:
- $(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck
- @echo
- @echo "Link check complete; look for any errors in the above output " \
- "or in $(BUILDDIR)/linkcheck/output.txt."
-
-doctest:
- $(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest
- @echo "Testing of doctests in the sources finished, look at the " \
- "results in $(BUILDDIR)/doctest/output.txt."
-
-xml:
- $(SPHINXBUILD) -b xml $(ALLSPHINXOPTS) $(BUILDDIR)/xml
- @echo
- @echo "Build finished. The XML files are in $(BUILDDIR)/xml."
-
-pseudoxml:
- $(SPHINXBUILD) -b pseudoxml $(ALLSPHINXOPTS) $(BUILDDIR)/pseudoxml
- @echo
- @echo "Build finished. The pseudo-XML files are in $(BUILDDIR)/pseudoxml."
+++ /dev/null
-@ECHO OFF
-
-REM Command file for Sphinx documentation
-
-if "%SPHINXBUILD%" == "" (
- set SPHINXBUILD=sphinx-build
-)
-set BUILDDIR=build
-set ALLSPHINXOPTS=-d %BUILDDIR%/doctrees %SPHINXOPTS% source
-set I18NSPHINXOPTS=%SPHINXOPTS% source
-if NOT "%PAPER%" == "" (
- set ALLSPHINXOPTS=-D latex_paper_size=%PAPER% %ALLSPHINXOPTS%
- set I18NSPHINXOPTS=-D latex_paper_size=%PAPER% %I18NSPHINXOPTS%
-)
-
-if "%1" == "" goto help
-
-if "%1" == "help" (
- :help
- echo.Please use `make ^<target^>` where ^<target^> is one of
- echo. html to make standalone HTML files
- echo. dirhtml to make HTML files named index.html in directories
- echo. singlehtml to make a single large HTML file
- echo. pickle to make pickle files
- echo. json to make JSON files
- echo. htmlhelp to make HTML files and a HTML help project
- echo. epub to make an epub
- echo. latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter
- echo. text to make text files
- echo. man to make manual pages
- echo. texinfo to make Texinfo files
- echo. gettext to make PO message catalogs
- echo. changes to make an overview over all changed/added/deprecated items
- echo. xml to make Docutils-native XML files
- echo. pseudoxml to make pseudoxml-XML files for display purposes
- echo. linkcheck to check all external links for integrity
- echo. doctest to run all doctests embedded in the documentation if enabled
- goto end
-)
-
-if "%1" == "clean" (
- for /d %%i in (%BUILDDIR%\*) do rmdir /q /s %%i
- del /q /s %BUILDDIR%\*
- goto end
-)
-
-
-%SPHINXBUILD% 2> nul
-if errorlevel 9009 (
- echo.
- echo.The 'sphinx-build' command was not found. Make sure you have Sphinx
- echo.installed, then set the SPHINXBUILD environment variable to point
- echo.to the full path of the 'sphinx-build' executable. Alternatively you
- echo.may add the Sphinx directory to PATH.
- echo.
- echo.If you don't have Sphinx installed, grab it from
- echo.http://sphinx-doc.org/
- exit /b 1
-)
-
-if "%1" == "html" (
- %SPHINXBUILD% -b html %ALLSPHINXOPTS% %BUILDDIR%/html
- if errorlevel 1 exit /b 1
- echo.
- echo.Build finished. The HTML pages are in %BUILDDIR%/html.
- goto end
-)
-
-if "%1" == "dirhtml" (
- %SPHINXBUILD% -b dirhtml %ALLSPHINXOPTS% %BUILDDIR%/dirhtml
- if errorlevel 1 exit /b 1
- echo.
- echo.Build finished. The HTML pages are in %BUILDDIR%/dirhtml.
- goto end
-)
-
-if "%1" == "singlehtml" (
- %SPHINXBUILD% -b singlehtml %ALLSPHINXOPTS% %BUILDDIR%/singlehtml
- if errorlevel 1 exit /b 1
- echo.
- echo.Build finished. The HTML pages are in %BUILDDIR%/singlehtml.
- goto end
-)
-
-if "%1" == "pickle" (
- %SPHINXBUILD% -b pickle %ALLSPHINXOPTS% %BUILDDIR%/pickle
- if errorlevel 1 exit /b 1
- echo.
- echo.Build finished; now you can process the pickle files.
- goto end
-)
-
-if "%1" == "json" (
- %SPHINXBUILD% -b json %ALLSPHINXOPTS% %BUILDDIR%/json
- if errorlevel 1 exit /b 1
- echo.
- echo.Build finished; now you can process the JSON files.
- goto end
-)
-
-if "%1" == "htmlhelp" (
- %SPHINXBUILD% -b htmlhelp %ALLSPHINXOPTS% %BUILDDIR%/htmlhelp
- if errorlevel 1 exit /b 1
- echo.
- echo.Build finished; now you can run HTML Help Workshop with the ^
-.hhp project file in %BUILDDIR%/htmlhelp.
- goto end
-)
-
-if "%1" == "epub" (
- %SPHINXBUILD% -b epub %ALLSPHINXOPTS% %BUILDDIR%/epub
- if errorlevel 1 exit /b 1
- echo.
- echo.Build finished. The epub file is in %BUILDDIR%/epub.
- goto end
-)
-
-if "%1" == "latex" (
- %SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex
- if errorlevel 1 exit /b 1
- echo.
- echo.Build finished; the LaTeX files are in %BUILDDIR%/latex.
- goto end
-)
-
-if "%1" == "latexpdf" (
- %SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex
- cd %BUILDDIR%/latex
- make all-pdf
- cd %BUILDDIR%/..
- echo.
- echo.Build finished; the PDF files are in %BUILDDIR%/latex.
- goto end
-)
-
-if "%1" == "latexpdfja" (
- %SPHINXBUILD% -b latex %ALLSPHINXOPTS% %BUILDDIR%/latex
- cd %BUILDDIR%/latex
- make all-pdf-ja
- cd %BUILDDIR%/..
- echo.
- echo.Build finished; the PDF files are in %BUILDDIR%/latex.
- goto end
-)
-
-if "%1" == "text" (
- %SPHINXBUILD% -b text %ALLSPHINXOPTS% %BUILDDIR%/text
- if errorlevel 1 exit /b 1
- echo.
- echo.Build finished. The text files are in %BUILDDIR%/text.
- goto end
-)
-
-if "%1" == "man" (
- %SPHINXBUILD% -b man %ALLSPHINXOPTS% %BUILDDIR%/man
- if errorlevel 1 exit /b 1
- echo.
- echo.Build finished. The manual pages are in %BUILDDIR%/man.
- goto end
-)
-
-if "%1" == "texinfo" (
- %SPHINXBUILD% -b texinfo %ALLSPHINXOPTS% %BUILDDIR%/texinfo
- if errorlevel 1 exit /b 1
- echo.
- echo.Build finished. The Texinfo files are in %BUILDDIR%/texinfo.
- goto end
-)
-
-if "%1" == "gettext" (
- %SPHINXBUILD% -b gettext %I18NSPHINXOPTS% %BUILDDIR%/locale
- if errorlevel 1 exit /b 1
- echo.
- echo.Build finished. The message catalogs are in %BUILDDIR%/locale.
- goto end
-)
-
-if "%1" == "changes" (
- %SPHINXBUILD% -b changes %ALLSPHINXOPTS% %BUILDDIR%/changes
- if errorlevel 1 exit /b 1
- echo.
- echo.The overview file is in %BUILDDIR%/changes.
- goto end
-)
-
-if "%1" == "linkcheck" (
- %SPHINXBUILD% -b linkcheck %ALLSPHINXOPTS% %BUILDDIR%/linkcheck
- if errorlevel 1 exit /b 1
- echo.
- echo.Link check complete; look for any errors in the above output ^
-or in %BUILDDIR%/linkcheck/output.txt.
- goto end
-)
-
-if "%1" == "doctest" (
- %SPHINXBUILD% -b doctest %ALLSPHINXOPTS% %BUILDDIR%/doctest
- if errorlevel 1 exit /b 1
- echo.
- echo.Testing of doctests in the sources finished, look at the ^
-results in %BUILDDIR%/doctest/output.txt.
- goto end
-)
-
-if "%1" == "xml" (
- %SPHINXBUILD% -b xml %ALLSPHINXOPTS% %BUILDDIR%/xml
- if errorlevel 1 exit /b 1
- echo.
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-)
-
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-
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-__version_full__ = __version__
-
-
-def get_html_theme_path():
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- return cur_dir
+++ /dev/null
-<div role="navigation" aria-label="breadcrumbs navigation">
-
- <div class="breadcrumb-box">
- <a class="breadcrumb-box-item" href="{{ pathto(master_doc) }}">Home</a>
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- <a class="breadcrumb-box-item" href="{{ doc.link|e }}">» {{ doc.title }}</a>
- {% endfor %}
- <div class="breadcrumb-box-item">» {{ title }}</div>
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-
-</div>
\ No newline at end of file
+++ /dev/null
-<footer>
- {% if next or prev %}
- <div class="rst-footer-buttons" role="navigation" aria-label="footer navigation">
- {% if next %}
- <a href="{{ next.link|e }}" class="btn btn-neutral float-right" title="{{ next.title|striptags|e }}"/>Next <span class="fa fa-arrow-circle-right"></span></a>
- {% endif %}
- {% if prev %}
- <a href="{{ prev.link|e }}" class="btn btn-neutral" title="{{ prev.title|striptags|e }}"><span class="fa fa-arrow-circle-left"></span> Previous</a>
- {% endif %}
- </div>
- {% endif %}
-
-
- <!--begin hamishw addition -->
-
-
-
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-
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- ('docs/introducing_litesata/license', 'Licensing', 'Licensing'),
- ('docs/contributing/contributing', 'Contributing', 'Contributing'),
- ('docs/introducing_litesata/release_notes', 'Release notes', 'Release notes'),
- ('docs/introducing_litesata/community', 'Help', 'Contact'),
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-
-
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- </li>
-
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-
- <p>
- {%- if show_copyright %}
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- {%- else %}
- <!-- {% trans copyright=copyright|e %}© Copyright {{ copyright }}.{% endtrans %} -->
- © Copyright {{ copyright }} <a href="{{ pathto("docs\contributing\AUTHORS") }}">HKU</a>.
- <!-- update theme to remove the translation stuff here - it was breaking due to link to AUTHORS file. This is a cludge to allow specific link to my authors file -->
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- {%- endif %}
-
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+++ /dev/null
-{# TEMPLATE VAR SETTINGS #}
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-{%- if not embedded and docstitle %}
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-
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-<head>
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-
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-
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-
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- {% if use_opensearch %}
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-
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- {%- endif %}
- <link rel="top" title="{{ docstitle|e }}" href="{{ pathto('index') }}"/>
- {%- if parents %}
- <link rel="up" title="{{ parents[-1].title|striptags|e }}" href="{{ parents[-1].link|e }}"/>
- {%- endif %}
- {%- if next %}
- <link rel="next" title="{{ next.title|striptags|e }}" href="{{ next.link|e }}"/>
- {%- endif %}
- {%- if prev %}
- <link rel="prev" title="{{ prev.title|striptags|e }}" href="{{ prev.link|e }}"/>
- {%- endif %}
- {%- endblock %}
- {%- block extrahead %} {% endblock %}
-
- {# Keep modernizr in head - http://modernizr.com/docs/#installing #}
- <script src="https://cdnjs.cloudflare.com/ajax/libs/modernizr/2.6.2/modernizr.min.js"></script>
-
-</head>
-
-<body class="wy-body-for-nav" role="document">
-
-
-<div class="grid-to-center-rtd-theme">
-
- <div class="wy-grid-for-nav">
-
-
-
- {# SIDE NAV, TOGGLES ON MOBILE #}
- <nav data-toggle="wy-nav-shift" class="wy-nav-side">
- <div class="wy-side-nav-search">
- <!-- <a href="{{ pathto(master_doc) }}" class="fa fa-home"> {{ project }}</a> -->
- <a href="{{ pathto(master_doc) }}"> <img src="{{ url_root }}/_static/{{ logo }}" alt="Logo" /> </a>
-
- {% include "searchbox.html" %}
- </div>
-
- <div class="wy-menu wy-menu-vertical" data-spy="affix" role="navigation" aria-label="main navigation">
-
- {% set toctree = toctree(maxdepth=4, collapse=False, includehidden=True) %}
- {% if toctree %}
- {{ toctree }}
- <a class="toctree-l1" title="Index" href="{{ pathto('genindex') }}">Index</a>
- {% else %}
- <!-- Local TOC -->
- <div class="local-toc">{{ toc }}</div>
- {% endif %}
- </div>
-
- </nav>
-
- <section data-toggle="wy-nav-shift" class="wy-nav-content-wrap">
-
- {# MOBILE NAV, TRIGGLES SIDE NAV ON TOGGLE #}
- <nav class="wy-nav-top" role="navigation" aria-label="top navigation">
- <i data-toggle="wy-nav-top" class="fa fa-bars"></i>
- <!-- <a href="{{ pathto(master_doc) }}">{{ project }}</a> -->
- <a href="{{ pathto(master_doc) }}"> <img src="{{ url_root }}/_static/{{ logo }}" alt="Logo" /> </a>
- </nav>
-
-
-
- {# PAGE CONTENT #}
- <div class="wy-nav-content">
- <div class="rst-content">
-
- <!--begin hamishw addition -->
-
- <!--Nav bar defined as a document followed by short version of nav text and long version
- If no such page exists then nav item is not created. CSS defines which of the long or short version is
- displayed. -->
- {% set navigation_bar = [
- ('docs/index', 'Docs', 'Documentation'),
- ('docs/getting_started/downloads', 'SDK', 'Downloads'),
- ('docs/introducing_litesata/community', 'Help', 'Community'),
- ('https://github.com/enjoy-digital/litesata', 'Github', 'Github Project')
-] -%}
-
-
- <div class="main-nav-bar" style="">
-
- <!-- the layout of the menu options - centered with left and right alignment of the first and last loop items respectively.
- This is VERY UGLY as I'm adding to the CSS in the code to force the alignment. Would be better just to have the elements here and have the CSS in the CSS file. This could be done with a CSS selector, but not worked out how yet. -->
-
- <ul id="menu-options">
- {% for document, shorttext, longtext in navigation_bar %}
- {%- if hasdoc(document) %}
- <li{%- if loop.first %} style="text-align:left;" {%- endif %}{%- if loop.last %} style="text-align:right;" {%- endif %}><a class="navlink-short" title="{{ shorttext }}" href="{{ pathto(document) }}">{{ shorttext }}</a><a class="navlink-long" title="{{ longtext }}" href="{{ pathto(document) }}">{{ longtext }}</a></li>
- {%- elif document | truncate(4, True, end='') == 'http' %}
- <li{%- if loop.first %} style="text-align:left;" {%- endif %}{%- if loop.last %} style="text-align:right;" {%- endif %}><a class="navlink-short external" href="{{ document }}">{{ shorttext }}</a><a class="navlink-long external" href="{{ document }}">{{ longtext }}</a></li>
- {%- endif %}
- {% endfor %}
- </ul>
- <!-- <div style="clear:both;"></div> -->
- {% include "breadcrumbs.html" %}
-
- </div>
-
-
-
- <!--end hamishw addition -->
-
- <!--HamishW move {% include "breadcrumbs.html" %} -->
- <div role="main">
- {% block body %}{% endblock %}
- </div>
- {% include "footer.html" %}
- </div>
- </div>
-
- </section>
-
- </div>
- {% include "versions.html" %}
-
- {% if not embedded %}
-
- <script type="text/javascript">
- var DOCUMENTATION_OPTIONS = {
- URL_ROOT:'{{ url_root }}',
- VERSION:'{{ release|e }}',
- COLLAPSE_INDEX:false,
- FILE_SUFFIX:'{{ '' if no_search_suffix else file_suffix }}',
- HAS_SOURCE: {{ has_source|lower }}
- };
- </script>
- {%- for scriptfile in script_files %}
- <script type="text/javascript" src="{{ pathto(scriptfile, 1) }}"></script>
- {%- endfor %}
-
- {% endif %}
-
- {# RTD hosts this file, so just load on non RTD builds #}
- {% if not READTHEDOCS %}
- <script type="text/javascript" src="{{ pathto('_static/js/theme.js', 1) }}"></script>
- {% endif %}
-
- {# STICKY NAVIGATION #}
- {% if theme_sticky_navigation %}
- <script type="text/javascript">
- jQuery(function () {
- SphinxRtdTheme.StickyNav.enable();
- });
- </script>
- {% endif %}
-
- {%- block footer %} {% endblock %}
-</div>
-</body>
-</html>
+++ /dev/null
-{#
- basic/layout.html
- ~~~~~~~~~~~~~~~~~
-
- Master layout template for Sphinx themes.
-
- :copyright: Copyright 2007-2013 by the Sphinx team, see AUTHORS.
- :license: BSD, see LICENSE for details.
-#}
-{%- block doctype -%}
-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
- "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
-{%- endblock %}
-{%- set reldelim1 = reldelim1 is not defined and ' »' or reldelim1 %}
-{%- set reldelim2 = reldelim2 is not defined and ' |' or reldelim2 %}
-{%- set render_sidebar = (not embedded) and (not theme_nosidebar|tobool) and
- (sidebars != []) %}
-{%- set url_root = pathto('', 1) %}
-{# XXX necessary? #}
-{%- if url_root == '#' %}{% set url_root = '' %}{% endif %}
-{%- if not embedded and docstitle %}
- {%- set titlesuffix = " — "|safe + docstitle|e %}
-{%- else %}
- {%- set titlesuffix = "" %}
-{%- endif %}
-
-{%- macro relbar() %}
- <div class="related">
- <h3>{{ _('Navigation') }}</h3>
- <ul>
- {%- for rellink in rellinks %}
- <li class="right" {% if loop.first %}style="margin-right: 10px"{% endif %}>
- <a href="{{ pathto(rellink[0]) }}" title="{{ rellink[1]|striptags|e }}"
- {{ accesskey(rellink[2]) }}>{{ rellink[3] }}</a>
- {%- if not loop.first %}{{ reldelim2 }}{% endif %}</li>
- {%- endfor %}
- {%- block rootrellink %}
- <li><a href="{{ pathto(master_doc) }}">{{ shorttitle|e }}</a>{{ reldelim1 }}</li>
- {%- endblock %}
- {%- for parent in parents %}
- <li><a href="{{ parent.link|e }}" {% if loop.last %}{{ accesskey("U") }}{% endif %}>{{ parent.title }}</a>{{ reldelim1 }}</li>
- {%- endfor %}
- {%- block relbaritems %} {% endblock %}
- </ul>
- </div>
-{%- endmacro %}
-
-{%- macro sidebar() %}
- {%- if render_sidebar %}
- <div class="sphinxsidebar">
- <div class="sphinxsidebarwrapper">
- {%- block sidebarlogo %}
- {%- if logo %}
- <p class="logo"><a href="{{ pathto(master_doc) }}">
- <img class="logo" src="{{ pathto('_static/' + logo, 1) }}" alt="Logo"/>
- </a></p>
- {%- endif %}
- {%- endblock %}
- {%- if sidebars != None %}
- {#- new style sidebar: explicitly include/exclude templates #}
- {%- for sidebartemplate in sidebars %}
- {%- include sidebartemplate %}
- {%- endfor %}
- {%- else %}
- {#- old style sidebars: using blocks -- should be deprecated #}
- {%- block sidebartoc %}
- {%- include "localtoc.html" %}
- {%- endblock %}
- {%- block sidebarrel %}
- {%- include "relations.html" %}
- {%- endblock %}
- {%- block sidebarsourcelink %}
- {%- include "sourcelink.html" %}
- {%- endblock %}
- {%- if customsidebar %}
- {%- include customsidebar %}
- {%- endif %}
- {%- block sidebarsearch %}
- {%- include "searchbox.html" %}
- {%- endblock %}
- {%- endif %}
- </div>
- </div>
- {%- endif %}
-{%- endmacro %}
-
-{%- macro script() %}
- <script type="text/javascript">
- var DOCUMENTATION_OPTIONS = {
- URL_ROOT: '{{ url_root }}',
- VERSION: '{{ release|e }}',
- COLLAPSE_INDEX: false,
- FILE_SUFFIX: '{{ '' if no_search_suffix else file_suffix }}',
- HAS_SOURCE: {{ has_source|lower }}
- };
- </script>
- {%- for scriptfile in script_files %}
- <script type="text/javascript" src="{{ pathto(scriptfile, 1) }}"></script>
- {%- endfor %}
-{%- endmacro %}
-
-{%- macro css() %}
- <link rel="stylesheet" href="{{ pathto('_static/' + style, 1) }}" type="text/css" />
- <link rel="stylesheet" href="{{ pathto('_static/pygments.css', 1) }}" type="text/css" />
- {%- for cssfile in css_files %}
- <link rel="stylesheet" href="{{ pathto(cssfile, 1) }}" type="text/css" />
- {%- endfor %}
-{%- endmacro %}
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <meta http-equiv="Content-Type" content="text/html; charset={{ encoding }}" />
- {{ metatags }}
- {%- block htmltitle %}
- <title>{{ title|striptags|e }}{{ titlesuffix }}</title>
- {%- endblock %}
- {{ css() }}
- {%- if not embedded %}
- {{ script() }}
- {%- if use_opensearch %}
- <link rel="search" type="application/opensearchdescription+xml"
- title="{% trans docstitle=docstitle|e %}Search within {{ docstitle }}{% endtrans %}"
- href="{{ pathto('_static/opensearch.xml', 1) }}"/>
- {%- endif %}
- {%- if favicon %}
- <link rel="shortcut icon" href="{{ pathto('_static/' + favicon, 1) }}"/>
- {%- endif %}
- {%- endif %}
-{%- block linktags %}
- {%- if hasdoc('about') %}
- <link rel="author" title="{{ _('About these documents') }}" href="{{ pathto('about') }}" />
- {%- endif %}
- {%- if hasdoc('genindex') %}
- <link rel="index" title="{{ _('Index') }}" href="{{ pathto('genindex') }}" />
- {%- endif %}
- {%- if hasdoc('search') %}
- <link rel="search" title="{{ _('Search') }}" href="{{ pathto('search') }}" />
- {%- endif %}
- {%- if hasdoc('copyright') %}
- <link rel="copyright" title="{{ _('Copyright') }}" href="{{ pathto('copyright') }}" />
- {%- endif %}
- <link rel="top" title="{{ docstitle|e }}" href="{{ pathto('index') }}" />
- {%- if parents %}
- <link rel="up" title="{{ parents[-1].title|striptags|e }}" href="{{ parents[-1].link|e }}" />
- {%- endif %}
- {%- if next %}
- <link rel="next" title="{{ next.title|striptags|e }}" href="{{ next.link|e }}" />
- {%- endif %}
- {%- if prev %}
- <link rel="prev" title="{{ prev.title|striptags|e }}" href="{{ prev.link|e }}" />
- {%- endif %}
-{%- endblock %}
-{%- block extrahead %} {% endblock %}
- </head>
- <body>
-{%- block header %}{% endblock %}
-
-{%- block relbar1 %}{{ relbar() }}{% endblock %}
-
-{%- block content %}
- {%- block sidebar1 %} {# possible location for sidebar #} {% endblock %}
-
- <div class="document">
- {%- block document %}
- <div class="documentwrapper">
- {%- if render_sidebar %}
- <div class="bodywrapper">
- {%- endif %}
- <div class="body">
- {% block body %} {% endblock %}
- </div>
- {%- if render_sidebar %}
- </div>
- {%- endif %}
- </div>
- {%- endblock %}
-
- {%- block sidebar2 %}{{ sidebar() }}{% endblock %}
- <div class="clearer"></div>
- </div>
-{%- endblock %}
-
-{%- block relbar2 %}{{ relbar() }}{% endblock %}
-
-{%- block footer %}
- <div class="footer">
- {%- if show_copyright %}
- {%- if hasdoc('copyright') %}
- {% trans path=pathto('copyright'), copyright=copyright|e %}© <a href="{{ path }}">Copyright</a> {{ copyright }}.{% endtrans %}
- {%- else %}
- {% trans copyright=copyright|e %}© Copyright {{ copyright }}.{% endtrans %}
- {%- endif %}
- {%- endif %}
- {%- if last_updated %}
- {% trans last_updated=last_updated|e %}Last updated on {{ last_updated }}.{% endtrans %}
- {%- endif %}
- {%- if show_sphinx %}
- {% trans sphinx_version=sphinx_version|e %}Created using <a href="http://sphinx-doc.org/">Sphinx</a> {{ sphinx_version }}.{% endtrans %}
- {%- endif %}
- </div>
- <p>asdf asdf asdf asdf 22</p>
-{%- endblock %}
- </body>
-</html>
-
+++ /dev/null
-{#
- basic/search.html
- ~~~~~~~~~~~~~~~~~
-
- Template for the search page.
-
- :copyright: Copyright 2007-2013 by the Sphinx team, see AUTHORS.
- :license: BSD, see LICENSE for details.
-#}
-{%- extends "layout.html" %}
-{% set title = _('Search') %}
-{% set script_files = script_files + ['_static/searchtools.js'] %}
-{% block footer %}
- <script type="text/javascript">
- jQuery(function() { Search.loadIndex("{{ pathto('searchindex.js', 1) }}"); });
- </script>
- {# this is used when loading the search index using $.ajax fails,
- such as on Chrome for documents on localhost #}
- <script type="text/javascript" id="searchindexloader"></script>
- {{ super() }}
-{% endblock %}
-{% block body %}
- <noscript>
- <div id="fallback" class="admonition warning">
- <p class="last">
- {% trans %}Please activate JavaScript to enable the search
- functionality.{% endtrans %}
- </p>
- </div>
- </noscript>
-
- {% if search_performed %}
- <h2>{{ _('Search Results') }}</h2>
- {% if not search_results %}
- <p>{{ _('Your search did not match any documents. Please make sure that all words are spelled correctly and that you\'ve selected enough categories.') }}</p>
- {% endif %}
- {% endif %}
- <div id="search-results">
- {% if search_results %}
- <ul>
- {% for href, caption, context in search_results %}
- <li>
- <a href="{{ pathto(item.href) }}">{{ caption }}</a>
- <p class="context">{{ context|e }}</p>
- </li>
- {% endfor %}
- </ul>
- {% endif %}
- </div>
-{% endblock %}
+++ /dev/null
-<div role="search">
- <form id ="rtd-search-form" class="wy-form" action="{{ pathto('search') }}" method="get">
- <input type="text" name="q" placeholder="Search docs" />
- <input type="hidden" name="check_keywords" value="yes" />
- <input type="hidden" name="area" value="default" />
- </form>
-</div>
+++ /dev/null
-.fa:before{-webkit-font-smoothing:antialiased}.clearfix{*zoom:1}.clearfix:before,.clearfix:after{display:table;content:""}.clearfix:after{clear:both}@font-face{font-family:FontAwesome;font-weight:normal;font-style:normal;src:url("../font/fontawesome_webfont.eot");src:url("../font/fontawesome_webfont.eot?#iefix") format("embedded-opentype"),url("../font/fontawesome_webfont.woff") format("woff"),url("../font/fontawesome_webfont.ttf") format("truetype"),url("../font/fontawesome_webfont.svg#FontAwesome") format("svg")}.fa:before{display:inline-block;font-family:FontAwesome;font-style:normal;font-weight:normal;line-height:1;text-decoration:inherit}a .fa{display:inline-block;text-decoration:inherit}li .fa{display:inline-block}li .fa-large:before,li .fa-large:before{width:1.875em}ul.fas{list-style-type:none;margin-left:2em;text-indent:-0.8em}ul.fas li .fa{width:0.8em}ul.fas li .fa-large:before,ul.fas li .fa-large:before{vertical-align:baseline}.fa-book:before{content:"\f02d"}.icon-book:before{content:"\f02d"}.fa-caret-down:before{content:"\f0d7"}.icon-caret-down:before{content:"\f0d7"}.fa-caret-up:before{content:"\f0d8"}.icon-caret-up:before{content:"\f0d8"}.fa-caret-left:before{content:"\f0d9"}.icon-caret-left:before{content:"\f0d9"}.fa-caret-right:before{content:"\f0da"}.icon-caret-right:before{content:"\f0da"}.rst-versions{position:fixed;bottom:0;left:0;width:300px;color:#fcfcfc;background:#1f1d1d;border-top:solid 10px #343131;font-family:"Lato","proxima-nova","Helvetica Neue",Arial,sans-serif;z-index:400}.rst-versions a{color:#2980b9;text-decoration:none}.rst-versions .rst-badge-small{display:none}.rst-versions .rst-current-version{padding:12px;background-color:#272525;display:block;text-align:right;font-size:90%;cursor:pointer;color:#27ae60;*zoom:1}.rst-versions .rst-current-version:before,.rst-versions .rst-current-version:after{display:table;content:""}.rst-versions .rst-current-version:after{clear:both}.rst-versions .rst-current-version .fa{color:#fcfcfc}.rst-versions .rst-current-version .fa-book{float:left}.rst-versions .rst-current-version .icon-book{float:left}.rst-versions .rst-current-version.rst-out-of-date{background-color:#e74c3c;color:#fff}.rst-versions .rst-current-version.rst-active-old-version{background-color:#f1c40f;color:#000}.rst-versions.shift-up .rst-other-versions{display:block}.rst-versions .rst-other-versions{font-size:90%;padding:12px;color:gray;display:none}.rst-versions .rst-other-versions hr{display:block;height:1px;border:0;margin:20px 0;padding:0;border-top:solid 1px #413d3d}.rst-versions .rst-other-versions dd{display:inline-block;margin:0}.rst-versions .rst-other-versions dd a{display:inline-block;padding:6px;color:#fcfcfc}.rst-versions.rst-badge{width:auto;bottom:20px;right:20px;left:auto;border:none;max-width:300px}.rst-versions.rst-badge .icon-book{float:none}.rst-versions.rst-badge .fa-book{float:none}.rst-versions.rst-badge.shift-up .rst-current-version{text-align:right}.rst-versions.rst-badge.shift-up .rst-current-version .fa-book{float:left}.rst-versions.rst-badge.shift-up .rst-current-version .icon-book{float:left}.rst-versions.rst-badge .rst-current-version{width:auto;height:30px;line-height:30px;padding:0 6px;display:block;text-align:center}@media screen and (max-width: 768px){.rst-versions{width:85%;display:none}.rst-versions.shift{display:block}img{width:100%;height:auto}}
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- .wy-breadcrumbs li a:first-child{padding-left:0}.wy-breadcrumbs-extra{margin-bottom:0;color:#b3b3b3;font-size:80%;display:inline-block}
-
- @media screen and (max-width: 480px)
- {.wy-breadcrumbs-extra{display:none}.wy-breadcrumbs li.wy-breadcrumbs-aside{display:none}}@media print{.wy-breadcrumbs li.wy-breadcrumbs-aside{display:none}}.wy-affix{position:fixed;top:1.618em}.wy-menu a:hover{text-decoration:none}.wy-menu-horiz{*zoom:1}.wy-menu-horiz:before,.wy-menu-horiz:after{display:table;content:""}.wy-menu-horiz:after{clear:both}.wy-menu-horiz ul,.wy-menu-horiz li{display:inline-block}.wy-menu-horiz li:hover{background:rgba(255,255,255,0.1)}.wy-menu-horiz li.divide-left{border-left:solid 1px #404040}.wy-menu-horiz li.divide-right{border-right:solid 1px #404040}.wy-menu-horiz a{height:32px;display:inline-block;line-height:32px;padding:0 16px}.wy-menu-vertical header{height:32px;display:inline-block;line-height:32px;padding:0 1.618em;display:block;font-weight:bold;text-transform:uppercase;font-size:80%;color:#2980b9;white-space:nowrap}.wy-menu-vertical ul{margin-bottom:0}.wy-menu-vertical li.divide-top{border-top:solid 1px #404040}.wy-menu-vertical li.divide-bottom{border-bottom:solid 1px #404040}.wy-menu-vertical li.current{background:#e3e3e3}
-
- .wy-menu-vertical li.current a{
- color:gray;
- border-right:solid 1px #c9c9c9;
- padding:0.4045em 2.427em
- }
-
- .wy-menu-vertical li.current a:hover{background:#d6d6d6}
-
- .wy-menu-vertical li.on a {
- color:#404040;
- padding:0.4045em 1.618em;
- font-weight:bold;
- position:relative;
- background:#fcfcfc;
- border:none;
- border-bottom:solid 1px #c9c9c9;
- border-top:solid 1px #c9c9c9;
- padding-left:1.618em -4px
- }
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-
-.wy-menu-vertical li.current>a {
- color:#404040;
- padding:0.4045em 1.618em;
- font-weight:bold;
- position:relative;
- background:#fcfcfc;
- border:none;
- border-bottom:solid 1px #c9c9c9;
- border-top:solid 1px #c9c9c9;
- padding-left:1.618em -4px
- }
-
- .wy-menu-vertical li.on a:hover,.wy-menu-vertical li.current>a:hover{background:#fcfcfc}
- .wy-menu-vertical li.toctree-l2.current>a{background:#c9c9c9;padding:0.4045em 2.427em}.wy-menu-vertical li.current ul{display:block}.wy-menu-vertical li ul{margin-bottom:0;display:none}.wy-menu-vertical .local-toc li ul{display:block}.wy-menu-vertical li ul li a{margin-bottom:0;color:#b3b3b3;font-weight:normal}.wy-menu-vertical a{display:inline-block;line-height:18px;padding:0.4045em 1.618em;display:block;position:relative;font-size:90%;color:#b3b3b3}.wy-menu-vertical a:hover{background-color:#4e4a4a;cursor:pointer}.wy-menu-vertical a:active{background-color:#2980b9;cursor:pointer;color:#fff}
-
- .wy-side-nav-search {z-index:200;
- background-color:#2980b9;
- text-align:center;
- /* padding:0.809em; */
- /* padding-top: 0.809em;*/
- padding-right: 0.809em;
- padding-bottom: 0.809em;
- padding-left: 0.809em;
- display:block;
- color:#fcfcfc;
- margin-bottom:0.809em
- }
-
- .wy-side-nav-search input[type=text]{width:100%;border-radius:50px;padding:6px 12px;border-color:#2472a4}
-
-
- .wy-side-nav-search img{
- display:block;
- margin:auto auto 0.809em auto;
- /*height:45px;*/
- /*width:45px;*/
- width:200px;
- /*background-color:#2980b9;*/
- padding:5px;
- /*border-radius:100%*/
- }
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- .wy-side-nav-search>a,.wy-side-nav-search .wy-dropdown>a {
- color:#fcfcfc;
- font-size:100%;
- font-weight:bold;
- display:inline-block;
- padding-top: 4px;
- padding-right: 6px;
- /*padding-bottom: 4px;*/
- padding-left: 6px;
- /* margin-bottom:0.809em */
- }
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- .wy-side-nav-search>a:hover,.wy-side-nav-search .wy-dropdown>a:hover{background:rgba(255,255,255,0.1)}.wy-nav .wy-menu-vertical header{color:#2980b9}.wy-nav .wy-menu-vertical a{color:#b3b3b3}.wy-nav .wy-menu-vertical a:hover{background-color:#2980b9;color:#fff}[data-menu-wrap]{-webkit-transition:all 0.2s ease-in;-moz-transition:all 0.2s ease-in;transition:all 0.2s ease-in;position:absolute;opacity:1;width:100%;opacity:0}[data-menu-wrap].move-center{left:0;right:auto;opacity:1}[data-menu-wrap].move-left{right:auto;left:-100%;opacity:0}[data-menu-wrap].move-right{right:-100%;left:auto;opacity:0}
-
- .wy-body-for-nav{
- /* background:left repeat-y #F1F0F0; */
- /*
- background:left repeat-y rgb(97, 6, 6);
- background-size:300px 1px
- */ /* This is deep red colour - removed */
- /* background-image:url(data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAEAAAABCAIAAACQd1PeAAAAGXRFWHRTb2Z0d2FyZQBBZG9iZSBJbWFnZVJlYWR5ccllPAAAAyRpVFh0WE1MOmNvbS5hZG9iZS54bXAAAAAAADw/eHBhY2tldCBiZWdpbj0i77u/IiBpZD0iVzVNME1wQ2VoaUh6cmVTek5UY3prYzlkIj8+IDx4OnhtcG1ldGEgeG1sbnM6eD0iYWRvYmU6bnM6bWV0YS8iIHg6eG1wdGs9IkFkb2JlIFhNUCBDb3JlIDUuMy1jMDExIDY2LjE0NTY2MSwgMjAxMi8wMi8wNi0xNDo1NjoyNyAgICAgICAgIj4gPHJkZjpSREYgeG1sbnM6cmRmPSJodHRwOi8vd3d3LnczLm9yZy8xOTk5LzAyLzIyLXJkZi1zeW50YXgtbnMjIj4gPHJkZjpEZXNjcmlwdGlvbiByZGY6YWJvdXQ9IiIgeG1sbnM6eG1wPSJodHRwOi8vbnMuYWRvYmUuY29tL3hhcC8xLjAvIiB4bWxuczp4bXBNTT0iaHR0cDovL25zLmFkb2JlLmNvbS94YXAvMS4wL21tLyIgeG1sbnM6c3RSZWY9Imh0dHA6Ly9ucy5hZG9iZS5jb20veGFwLzEuMC9zVHlwZS9SZXNvdXJjZVJlZiMiIHhtcDpDcmVhdG9yVG9vbD0iQWRvYmUgUGhvdG9zaG9wIENTNiAoTWFjaW50b3NoKSIgeG1wTU06SW5zdGFuY2VJRD0ieG1wLmlpZDoxOERBMTRGRDBFMUUxMUUzODUwMkJCOThDMEVFNURFMCIgeG1wTU06RG9jdW1lbnRJRD0ieG1wLmRpZDoxOERBMTRGRTBFMUUxMUUzODUwMkJCOThDMEVFNURFMCI+IDx4bXBNTTpEZXJpdmVkRnJvbSBzdFJlZjppbnN0YW5jZUlEPSJ4bXAuaWlkOjE4REExNEZCMEUxRTExRTM4NTAyQkI5OEMwRUU1REUwIiBzdFJlZjpkb2N1bWVudElEPSJ4bXAuZGlkOjE4REExNEZDMEUxRTExRTM4NTAyQkI5OEMwRUU1REUwIi8+IDwvcmRmOkRlc2NyaXB0aW9uPiA8L3JkZjpSREY+IDwveDp4bXBtZXRhPiA8P3hwYWNrZXQgZW5kPSJyIj8+EwrlwAAAAA5JREFUeNpiMDU0BAgwAAE2AJgB9BnaAAAAAElFTkSuQmCC); */
-
- }
-
- .wy-grid-for-nav {
- /* position:absolute; */
- position:relative; /* Make left column full length */
- width:100%;
- height:100%
- }
-
- .wy-nav-side{position:absolute;top:0;left:0;width:300px;overflow:hidden;min-height:100%;background:#343131;z-index:200}
-
- .wy-nav-top{
- display:none;
- background:#2980b9;
- color:#fff;
- padding:0.4045em 0.809em;
- position:relative;
- line-height:50px;
- text-align:center;
- font-size:100%;
- *zoom:1}
-
- .wy-nav-top:before,.wy-nav-top:after{display:table;content:""}
-
- .wy-nav-top:after{clear:both}.wy-nav-top a{color:#fff;font-weight:bold}
-
- .wy-nav-top img{
- margin-right:12px;
- /*height:45px; */
- /*width:45px;*/
- width:200px;
- background-color:#2980b9;
- padding:5px;
- /*border-radius:100%*/
- }
-
- .wy-nav-top i{font-size:30px;float:left;cursor:pointer}
- .wy-nav-content-wrap{
- margin-left:300px;
- /* background:#fcfcfc; */
- min-height:100%
- }
-
- .wy-nav-content{
- /* padding:1.618em 3.236em; */
- /* padding-top: 1.618em; */
- padding-right: 3.236em;
- padding-bottom: 1.618em;
- padding-left: 3.236em;
- height:100%;
- min-height: 100vh; /* ensure is always full height of browser window */
- max-width:800px;
- /* margin:auto; */
- margin-left:0px;
- background: #fcfcfc;
- }
-
- .wy-body-mask{position:fixed;width:100%;height:100%;background:rgba(0,0,0,0.2);display:none;z-index:499}.wy-body-mask.on{display:block}footer{color:#999}footer p{margin-bottom:12px}.rst-footer-buttons{*zoom:1}.rst-footer-buttons:before,.rst-footer-buttons:after{display:table;content:""}.rst-footer-buttons:after{clear:both}#search-results .search li{margin-bottom:24px;border-bottom:solid 1px #e1e4e5;padding-bottom:24px}#search-results .search li:first-child{border-top:solid 1px #e1e4e5;padding-top:24px}#search-results .search li a{font-size:120%;margin-bottom:12px;display:inline-block}#search-results .context{color:gray;font-size:90%}
-
- @media screen and (max-width: 768px){
- .wy-body-for-nav{background:#fcfcfc}
- .wy-nav-top{display:block}.wy-nav-side{left:-300px}
- .wy-nav-side.shift{width:85%;left:0}
- .wy-nav-content-wrap{margin-left:0}
- .wy-nav-content-wrap .wy-nav-content {
- /* padding:1.618em */
- /* padding-top: 1.618em; */
- padding-right: 1.618em;
- padding-bottom: 1.618em;
- padding-left: 1.618em;
- }
- .wy-nav-content-wrap.shift{
- position:relative; /* position:fixed; */
- min-width:100%;
- left:85%;
- top:0;height:100%;
- overflow:hidden
- }
- }
-
- @media screen and (min-width: 1400px) {
- /* .wy-nav-content-wrap{background:rgba(0,0,0,0.05)} */
- .wy-nav-content{
- /* margin:0; */
- background:#fcfcfc}
- }
-
- @media print{.wy-nav-side{display:none}.wy-nav-content-wrap{margin-left:0}}nav.stickynav{position:absolute/* previously fixed hamishw */ ;top:0}.rst-versions{position:fixed;bottom:0;left:0;width:300px;color:#fcfcfc;background:#1f1d1d;border-top:solid 10px #343131;font-family:"Lato","proxima-nova","Helvetica Neue",Arial,sans-serif;z-index:400}.rst-versions a{color:#2980b9;text-decoration:none}.rst-versions .rst-badge-small{display:none}.rst-versions .rst-current-version{padding:12px;background-color:#272525;display:block;text-align:right;font-size:90%;cursor:pointer;color:#27ae60;*zoom:1}.rst-versions .rst-current-version:before,.rst-versions .rst-current-version:after{display:table;content:""}.rst-versions .rst-current-version:after{clear:both}.rst-versions .rst-current-version .fa,.rst-versions .rst-current-version .rst-content .admonition-title,.rst-content .rst-versions .rst-current-version .admonition-title,.rst-versions .rst-current-version .rst-content h1 .headerlink,.rst-content h1 .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .rst-content h2 .headerlink,.rst-content h2 .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .rst-content h3 .headerlink,.rst-content h3 .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .rst-content h4 .headerlink,.rst-content h4 .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .rst-content h5 .headerlink,.rst-content h5 .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .rst-content h6 .headerlink,.rst-content h6 .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .rst-content dl dt .headerlink,.rst-content dl dt .rst-versions .rst-current-version .headerlink,.rst-versions .rst-current-version .icon{color:#fcfcfc}.rst-versions .rst-current-version .fa-book,.rst-versions .rst-current-version .icon-book{float:left}.rst-versions .rst-current-version .icon-book{float:left}.rst-versions .rst-current-version.rst-out-of-date{background-color:#e74c3c;color:#fff}.rst-versions .rst-current-version.rst-active-old-version{background-color:#f1c40f;color:#000}.rst-versions.shift-up .rst-other-versions{display:block}.rst-versions .rst-other-versions{font-size:90%;padding:12px;color:gray;display:none}.rst-versions .rst-other-versions hr{display:block;height:1px;border:0;margin:20px 0;padding:0;border-top:solid 1px #413d3d}.rst-versions .rst-other-versions dd{display:inline-block;margin:0}.rst-versions .rst-other-versions dd a{display:inline-block;padding:6px;color:#fcfcfc}.rst-versions.rst-badge{width:auto;bottom:20px;right:20px;left:auto;border:none;max-width:300px}.rst-versions.rst-badge .icon-book{float:none}.rst-versions.rst-badge .fa-book,.rst-versions.rst-badge .icon-book{float:none}.rst-versions.rst-badge.shift-up .rst-current-version{text-align:right}.rst-versions.rst-badge.shift-up .rst-current-version .fa-book,.rst-versions.rst-badge.shift-up .rst-current-version .icon-book{float:left}.rst-versions.rst-badge.shift-up .rst-current-version .icon-book{float:left}.rst-versions.rst-badge .rst-current-version{width:auto;height:30px;line-height:30px;padding:0 6px;display:block;text-align:center}
-
- @media screen and (max-width: 768px){
- .rst-versions{width:85%;display:none}.rst-versions.shift{display:block}img{width:100%;height:auto}}.rst-content img{max-width:100%;height:auto !important}.rst-content div.figure{margin-bottom:24px}.rst-content div.figure.align-center{text-align:center}.rst-content .section>img{margin-bottom:24px}.rst-content blockquote{margin-left:24px;line-height:24px;margin-bottom:24px}.rst-content .note .last,.rst-content .attention .last,.rst-content .caution .last,.rst-content .danger .last,.rst-content .error .last,.rst-content .hint .last,.rst-content .important .last,.rst-content .tip .last,.rst-content .warning .last,.rst-content .seealso .last{margin-bottom:0}.rst-content .admonition-title:before{margin-right:4px}.rst-content .admonition table{border-color:rgba(0,0,0,0.1)}.rst-content .admonition table td,.rst-content .admonition table th{background:transparent !important;border-color:rgba(0,0,0,0.1) !important}.rst-content .section ol.loweralpha,.rst-content .section ol.loweralpha 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dt:first-child{margin-top:0}.rst-content dl:not(.docutils) tt{font-weight:bold}.rst-content dl:not(.docutils) tt.descname,.rst-content dl:not(.docutils) tt.descclassname{background-color:transparent;border:none;padding:0;font-size:100% !important}.rst-content dl:not(.docutils) tt.descname{font-weight:bold}.rst-content dl:not(.docutils) .optional{display:inline-block;padding:0 4px;color:#000;font-weight:bold}.rst-content dl:not(.docutils) .property{display:inline-block;padding-right:8px}.rst-content .viewcode-link,.rst-content .viewcode-back{display:inline-block;color:#27ae60;font-size:80%;padding-left:24px}.rst-content .viewcode-back{display:block;float:right}
-
- @media screen and (max-width: 480px){
- .rst-content .sidebar{width:100%}}span[id*='MathJax-Span']{color:#404040}
-/*!
- * HamishW - some CSS for nav bar
- */
-
-.main-nav-bar {
- display:block;
- max-width: 1100px;
- border-bottom: solid;
- border-bottom-width: thin;
- padding-bottom: 10px;
- margin-bottom:20px;
- padding-top: 10px;
-}
-
-
-#menu-options {
- display: table;
- /* background-color:#F8F8F8; */
- /*height: 87px;*/
-
- width: 100%;
-}
-
-#menu-options li {
- display: table-cell;
- /* padding-left: 5px;
- padding-right: 5px; */
- padding-top: 10px;
- padding-bottom: 10px;
- width: 5.0%; /*(100 / numItems)% */
- text-align: center;
- font-weight:bold;
- /*background: #ddd;*/
- white-space: nowrap;
-}​
-
-
-
-.navlink-long {
- display:inline-block;
- vertical-align: top;
- padding:5px;
-}
-
-.navlink-short {
- display:none;
- vertical-align: top;
- padding:5px;
-}
-
-
-.footer-nav-bar {
- display:block;
- background-color:#F8F8F8;
- max-width: 1100px;
- /*border-bottom: solid;*/
- padding-bottom: 10px;
- margin-top:15px;
- border-top:solid;
- /* border-top-width:thin; */
-}
-
-.footer-options {
-/* display:block;
-width:inherit;
-font-size:0.8em;
-font-weight:normal;
-*/
-display:block;
-text-align:justify;
-font-size:0.8em;
-width:inherit;
-}
-
-.footer-navlink-long {
- display: inline-block;
- vertical-align: top;
- padding:5px;
-}
-
-.footer-navlink-short {
- display:none;
- padding:5px;
-}
-
-.footer-options:after {
- content: "";
- width: 100%;
- line-height:1px;
- line-spacing:1px;
- display: inline-block;
- }
-
-.copyright-box {
- border-top:solid;
- border-top-width:thin;
- margin-top:10px;
- background-color:#F8F8F8;
- padding-bottom:5px;
-
-}
-
-.copyright-box p {
- font-size:0.8em;
-}
-
-
-
-/* HamishW - Attempt to wrap table columns/remove the "responsive" behaviour on some tables. */
-table.wrap-table-content td, table.wrap-table-content th {
- white-space: normal;
-}
-
-
-
-/* HamishW - add clear markup for external links */
-
-a.external:after {
- content: "";
- display: inline-block;
- background-image: url(data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAwAAAAMCAYAAABWdVznAAAAV0lEQVR4Xq2QwQ2AAAwC3cmd2Kk7sRP64CEJ9qOX8OPatMc/QKppnEPhTmJh23CLiwAqIw21CybKQ28qQi37WGFYBJcwfJQpP8LlEHKyZMF0IdmF13zlAjZ/6H4wb+mUAAAAAElFTkSuQmCC);
- background-repeat: no-repeat;
- background-position: right top;
- background-origin: border-box;
- width: 12px;
- height: 16px;
-}
-
-
-/* HamishW - some CSS for the breadcrumb (make elements inline blocks) */
-
-
-.breadcrumb-box {
- margin-top:10px;
- font-size:0.8em;
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- $("[data-toggle='wy-nav-shift']").toggleClass("shift");
- $("[data-toggle='rst-versions']").toggleClass("shift");
- });
- // Close menu when you click a link.
- $(document).on('click', ".wy-menu-vertical .current ul li a", function() {
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- $("[data-toggle='rst-versions']").toggleClass("shift");
- });
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- $("[data-toggle='rst-versions']").toggleClass("shift-up");
- });
- // Make tables responsive
- $("table.docutils:not(.field-list)").wrap("<div class='wy-table-responsive'></div>");
-});
-
-window.SphinxRtdTheme = (function (jquery) {
- var stickyNav = (function () {
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- win,
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-[theme]
-inherit = basic
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-[options]
-typekit_id = hiw1hhg
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-sticky_navigation = True
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+++ /dev/null
-{% if READTHEDOCS %}
-{# Add rst-badge after rst-versions for small badge style. #}
- <div class="rst-versions" data-toggle="rst-versions" role="note" aria-label="versions">
- <span class="rst-current-version" data-toggle="rst-current-version">
- <span class="fa fa-book"> Read the Docs</span>
- v: {{ current_version }}
- <span class="fa fa-caret-down"></span>
- </span>
- <div class="rst-other-versions">
- <dl>
- <dt>Versions</dt>
- {% for slug, url in versions %}
- <dd><a href="{{ url }}">{{ slug }}</a></dd>
- {% endfor %}
- </dl>
- <dl>
- <dt>Downloads</dt>
- {% for type, url in downloads %}
- <dd><a href="{{ url }}">{{ type }}</a></dd>
- {% endfor %}
- </dl>
- <dl>
- <dt>On Read the Docs</dt>
- <dd>
- <a href="//{{ PRODUCTION_DOMAIN }}/projects/{{ slug }}/?fromdocs={{ slug }}">Project Home</a>
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- <dd>
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- <hr/>
- Free document hosting provided by <a href="http://www.readthedocs.org">Read the Docs</a>.
-
- </div>
- </div>
-{% endif %}
-
+++ /dev/null
-# -*- coding: utf-8 -*-
-#
-# LiteSATA documentation build configuration file, created by
-# sphinx-quickstart on Tue Jul 01 09:20:29 2014.
-#
-# This file is execfile()d with the current directory set to its
-# containing dir.
-#
-# Note that not all possible configuration values are present in this
-# autogenerated file.
-#
-# All configuration values have a default; values that are commented out
-# serve to show the default.
-
-import sys
-import os
-
-
-# At the top. #HamishW https://pypi.python.org/pypi/sphinx-bootstrap-theme/ ...
-#import sphinx_bootstrap_theme
-
-
-# At the top. #HamishW http://sphinx-better-theme.readthedocs.org/en/latest/installation.html easy_install sphinx_better_theme
-#from better import better_theme_path
-#html_theme_path = [better_theme_path]
-
-
-# At the top. #HamishW https://github.com/snide/sphinx_rtd_theme easy_install sphinx_rtd_theme
-#import sphinx_rtd_theme
-#html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
-
-html_theme_path = ['_themes',]
-
-
-
-
-
-
-
-# If extensions (or modules to document with autodoc) are in another directory,
-# add these directories to sys.path here. If the directory is relative to the
-# documentation root, use os.path.abspath to make it absolute, like shown here.
-#sys.path.insert(0, os.path.abspath('.'))
-
-
-# -- General configuration ------------------------------------------------
-
-# If your documentation needs a minimal Sphinx version, state it here.
-#needs_sphinx = '1.0'
-
-# Add any Sphinx extension module names here, as strings. They can be
-# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
-# ones.
-extensions = [
- 'sphinx.ext.autodoc',
- 'sphinx.ext.doctest',
- 'sphinx.ext.intersphinx',
- 'sphinx.ext.todo',
- 'sphinx.ext.coverage',
- 'sphinx.ext.ifconfig',
- 'sphinx.ext.viewcode',
- # 'breathe', #added by HamishW
-]
-
-
-#Build "Todo" notes into the source
-#todo_include_todos = 'True'
-
-# Add any paths that contain templates here, relative to this directory.
-templates_path = ['_templates']
-
-# The suffix of source filenames.
-source_suffix = '.rst'
-
-# The encoding of source files.
-#source_encoding = 'utf-8-sig'
-
-# The master toctree document.
-master_doc = 'index'
-
-# General information about the project.
-project = u'LiteSATA'
-copyright = u'2015, '
- # Note, theme was modified to allow this to display (fix breaks the translation code, which was breaking the above link and rendering it as text).
- # Also so I could link to specific copyright page.
-
-
-# The version info for the project you're documenting, acts as replacement for
-# |version| and |release|, also used in various other places throughout the
-# built documents.
-#
-
-litesata_version = open(os.path.abspath(os.path.join(os.path.dirname(os.path.dirname(os.path.dirname(__file__))), 'litesata-version.txt'))).read().strip()
-
-# The short X.Y version.
-version = litesata_version[:litesata_version.rindex('.')]
-# The full version, including alpha/beta/rc tags.
-release = litesata_version
-
-# The language for content autogenerated by Sphinx. Refer to documentation
-# for a list of supported languages.
-#language = None
-
-# There are two options for replacing |today|: either, you set today to some
-# non-false value, then it is used:
-#today = ''
-# Else, today_fmt is used as the format for a strftime call.
-#today_fmt = '%B %d, %Y'
-
-# List of patterns, relative to source directory, that match files and
-# directories to ignore when looking for source files.
-exclude_patterns = []
-
-# The reST default role (used for this markup: `text`) to use for all
-# documents.
-#default_role = None
-
-# If true, '()' will be appended to :func: etc. cross-reference text.
-#add_function_parentheses = True
-
-# If true, the current module name will be prepended to all description
-# unit titles (such as .. function::).
-#add_module_names = True
-
-# If true, sectionauthor and moduleauthor directives will be shown in the
-# output. They are ignored by default.
-#show_authors = False
-
-# The name of the Pygments (syntax highlighting) style to use.
-pygments_style = 'sphinx'
-
-# A list of ignored prefixes for module index sorting.
-#modindex_common_prefix = []
-
-# If true, keep warnings as "system message" paragraphs in the built documents.
-#keep_warnings = False
-
-
-# -- Options for HTML output ----------------------------------------------
-
-# The theme to use for HTML and HTML Help pages. See the documentation for
-# a list of builtin themes.
-#html_theme = 'default'
-#html_theme = 'sphinxdoc'
-#html_theme = 'agogo' #like this
-#html_theme = 'scrolls'
-#html_theme = 'bootstrap'
-#html_theme_path = sphinx_bootstrap_theme.get_html_theme_path()
-#html_theme = 'better'
-#html_theme = 'pyramid'
-#html_theme = 'nature'
-#html_theme = 'haiku'
-#html_theme = "sphinx_rtd_theme"
-html_theme = "enjoydigital_sphinx_rtd_theme"
-
-# Theme options are theme-specific and customize the look and feel of a theme
-# further. For a list of options available for each theme, see the
-# documentation.
-#html_theme_options = {
-# "rightsidebar": "true",
-# "relbarbgcolor": "black"
-#}
-
-
-# Add any paths that contain custom themes here, relative to this directory.
-#html_theme_path = []
-
-# The name for this set of Sphinx documents. If None, it defaults to
-# "<project> v<release> documentation".
-#html_title = None
-
-# A shorter title for the navigation bar. Default is the same as html_title.
-#html_short_title = None
-
-# The name of an image file (relative to this directory) to place at the top
-# of the sidebar.
-html_logo = '_static/LiteSATA_logo_full.png'
-
-
-# The name of an image file (within the static path) to use as favicon of the
-# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32
-# pixels large.
-html_favicon = 'litesata.ico'
-
-# Add any paths that contain custom static files (such as style sheets) here,
-# relative to this directory. They are copied after the builtin static files,
-# so a file named "default.css" will overwrite the builtin "default.css".
-html_static_path = ['_static']
-
-# Add any extra paths that contain custom files (such as robots.txt or
-# .htaccess) here, relative to this directory. These files are copied
-# directly to the root of the documentation.
-#html_extra_path = []
-
-# If not '', a 'Last updated on:' timestamp is inserted at every page bottom,
-# using the given strftime format.
-#html_last_updated_fmt = '%b %d, %Y'
-
-# If true, SmartyPants will be used to convert quotes and dashes to
-# typographically correct entities.
-#html_use_smartypants = True
-
-# Custom sidebar templates, maps document names to template names.
-#html_sidebars = {}
-
-# Additional templates that should be rendered to pages, maps page names to
-# template names.
-#html_additional_pages = {}
-
-# If false, no module index is generated.
-#html_domain_indices = True
-
-# If false, no index is generated.
-#html_use_index = True
-
-# If true, the index is split into individual pages for each letter.
-#html_split_index = False
-
-# If true, links to the reST sources are added to the pages.
-#html_show_sourcelink = True
-
-# If true, "Created using Sphinx" is shown in the HTML footer. Default is True.
-#html_show_sphinx = True
-
-# If true, "(C) Copyright ..." is shown in the HTML footer. Default is True.
-#html_show_copyright = True
-
-# If true, an OpenSearch description file will be output, and all pages will
-# contain a <link> tag referring to it. The value of this option must be the
-# base URL from which the finished HTML is served.
-#html_use_opensearch = ''
-
-# This is the file name suffix for HTML files (e.g. ".xhtml").
-#html_file_suffix = None
-
-# Output file base name for HTML help builder.
-htmlhelp_basename = 'LiteSATAdoc'
-
-
-# -- Options for LaTeX output ---------------------------------------------
-
-latex_elements = {
-# The paper size ('letterpaper' or 'a4paper').
-#'papersize': 'letterpaper',
-
-# The font size ('10pt', '11pt' or '12pt').
-#'pointsize': '10pt',
-
-# Additional stuff for the LaTeX preamble.
-#'preamble': '',
-}
-
-# Grouping the document tree into LaTeX files. List of tuples
-# (source start file, target name, title,
-# author, documentclass [howto, manual, or own class]).
-latex_documents = [
- ('index', 'LiteSATA.tex', u'LiteSATA Documentation',
- u'Kermarrec Florent', 'manual'),
-]
-
-# The name of an image file (relative to this directory) to place at the top of
-# the title page.
-#latex_logo = None
-
-# For "manual" documents, if this is true, then toplevel headings are parts,
-# not chapters.
-#latex_use_parts = False
-
-# If true, show page references after internal links.
-#latex_show_pagerefs = False
-
-# If true, show URL addresses after external links.
-#latex_show_urls = False
-
-# Documents to append as an appendix to all manuals.
-#latex_appendices = []
-
-# If false, no module index is generated.
-#latex_domain_indices = True
-
-
-# -- Options for manual page output ---------------------------------------
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
- ('index', 'litesata', u'LiteSATA Documentation',
- [u'Florent Kermarrec'], 1)
-]
-
-# If true, show URL addresses after external links.
-#man_show_urls = False
-
-
-# -- Options for Texinfo output -------------------------------------------
-
-# Grouping the document tree into Texinfo files. List of tuples
-# (source start file, target name, title, author,
-# dir menu entry, description, category)
-texinfo_documents = [
- ('index', 'LiteSATA', u'LiteSATA Documentation',
- u'Florent Kermarrec', 'LiteSATA', 'One line description of project.',
- 'Miscellaneous'),
-]
-
-# Documents to append as an appendix to all manuals.
-#texinfo_appendices = []
-
-# If false, no module index is generated.
-#texinfo_domain_indices = True
-
-# How to display URL addresses: 'footnote', 'no', or 'inline'.
-#texinfo_show_urls = 'footnote'
-
-# If true, do not generate a @detailmenu in the "Top" node's menu.
-#texinfo_no_detailmenu = False
-
-
-# -- Options for Epub output ----------------------------------------------
-
-# Bibliographic Dublin Core info.
-epub_title = u'LiteSATA'
-epub_author = u'Florent Kermarrec'
-epub_publisher = u'Florent Kermarrec'
-epub_copyright = u'2015, LiteSATA Contributors'
-
-# The basename for the epub file. It defaults to the project name.
-#epub_basename = u'LiteSATA'
-
-# The HTML theme for the epub output. Since the default themes are not optimized
-# for small screen space, using the same theme for HTML and epub output is
-# usually not wise. This defaults to 'epub', a theme designed to save visual
-# space.
-#epub_theme = 'epub'
-
-# The language of the text. It defaults to the language option
-# or en if the language is not set.
-#epub_language = ''
-
-# The scheme of the identifier. Typical schemes are ISBN or URL.
-#epub_scheme = ''
-
-# The unique identifier of the text. This can be a ISBN number
-# or the project homepage.
-#epub_identifier = ''
-
-# A unique identification for the text.
-#epub_uid = ''
-
-# A tuple containing the cover image and cover page html template filenames.
-#epub_cover = ()
-
-# A sequence of (type, uri, title) tuples for the guide element of content.opf.
-#epub_guide = ()
-
-# HTML files that should be inserted before the pages created by sphinx.
-# The format is a list of tuples containing the path and title.
-#epub_pre_files = []
-
-# HTML files shat should be inserted after the pages created by sphinx.
-# The format is a list of tuples containing the path and title.
-#epub_post_files = []
-
-# A list of files that should not be packed into the epub file.
-epub_exclude_files = ['search.html']
-
-# The depth of the table of contents in toc.ncx.
-#epub_tocdepth = 3
-
-# Allow duplicate toc entries.
-#epub_tocdup = True
-
-# Choose between 'default' and 'includehidden'.
-#epub_tocscope = 'default'
-
-# Fix unsupported image types using the PIL.
-#epub_fix_images = False
-
-# Scale large images.
-#epub_max_image_width = 0
-
-# How to display URL addresses: 'footnote', 'no', or 'inline'.
-#epub_show_urls = 'inline'
-
-# If false, no index is generated.
-#epub_use_index = True
-
-
-# Example configuration for intersphinx: refer to the Python standard library.
-intersphinx_mapping = {'http://docs.python.org/': None}
-
-# HamishW - set highlighting language.
-highlight_language = 'cpp'
-
-# HamishW - set domain (cpp)
-primary_domain = 'cpp'
-
-# HamishW - tell Breathe about projects. Breathe is tool to convert Doxygen to Python objects, for import into Sphinx.
-#breathe_projects = { "myproject": "/home/me/docproj/doxyxml/", "nutshell":"./headers/xml/", }
-# HamishW - Specify a default project:
-#breathe_default_project = "nutshell"
-
+++ /dev/null
-.. _core-index:
-
-========================
-Core
-========================
-.. note::
- Please contribute to this document, or support us financially to write it.
\ No newline at end of file
+++ /dev/null
-.. _frontend-index:
-
-===================
-Frontend interfaces
-===================
-
-All frontend modules of LiteSATA share the same user interface based on packets.
-An interface has 2 endpoints:
-
- - A Sink used to send commands and write data.
- - A Source used to receive commands acknowledges and read data.
-
-Packets and user commands/responses are described in the next sections.
-
-Packet description
-==================
-
-Sink and Source endpoints use packets with additional parameters. A packet has the following signals:
-
- - :code:`stb`: Strobe signal, indicates that command or data is valid.
- - :code:`sop`: Start Of Packet signal, indicates that current command or data is the first of the packet.
- - :code:`eop`: End Of Packet signal, indicates that current command or data is the last of the packet.
- - :code:`ack`: Acknowledge signal, indicates the destination is able to accept current data.
- - :code:`data`: Data signal.
-
-.. figure:: packets.png
- :width: 50%
- :align: center
-
- An example of packet transaction between endpoints.
-
-.. tip::
-
- - When a packet only has a :code:`data`, :code:`sop` and :code:`eop` must be set to 1 on the same clock cycle.
- - A :code:`data` is accepted when :code:`stb` =1 and :code:`ack` =1.
-
-User Commands
-=============
-
-All transfers are initiated using the Sink endpoint of the interface which has the following signals:
-
- - :code:`write`: 1 bit signal, indicates if we want to write data to the HDD.
- - :code:`read`: 1 bit signal, indicates if we want to read data from the HDD.
- - :code:`identify`: 1 bit signal, indicates if the command is an identify device command (use to get HDD information).
- - :code:`sector`: 48 bits signal, the sector number we are going to write or read.
- - :code:`count`: 16 bits signal, the number of sectors we are going to write or read.
- - :code:`data`: n x 32 bits signal, the write data. (n depends of the frontend module)
-
-.. tip::
-
- - :code:`write`, :code:`read`, :code:`identify`, :code:`sector`, :code:`count` are parameters which must remain constant for the duration of the packet.
- - :code:`sector`, :code:`count` are ignored during an :code:`identify` command.
- - :code:`data` is ignored during a :code:`read` or :code:`identify` command.
-
-User Responses
-==============
-
-Responses are obtained from the Source endpoint which has the following signals:
-
- - :code:`write`: 1 bit signal, indicates if the command was a write.
- - :code:`read`: 1 bit signal, indicates if the command was a read.
- - :code:`identify`: 1 bit signal, indicates if the command was an identify device command.
- - :code:`last`: 1 bit signal, indicates if this is the last packet of the response. (A response can be return in several packets)
- - :code:`failed`: 1 bit signal, indicates if an error was detected in the response (CRC, FIS...)
- - :code:`data`: n x 32 bits signal, the read data. (n depends of the frontend module)
-
-.. tip::
-
- - :code:`write`, :code:`read`, :code:`identify`, :code:`last` are parameters that must remain constant for the duration of a packet.
- - :code:`data` can be ignored in the case of a :code:`write` or :code:`identify` command.
- - in case of a :code:`read` command, read data packets are presented followed by an empty packet indicating the end of the transaction (last=1).
-
-================
-Frontend modules
-================
-
-LiteSATA provides a configurable and flexible frontend that can be used to:
-
-- Provides any number of user ports.
-- Generate RAID configurations when used with multiple HDDs.
-
-Crossbar
-========
-
-The crossbar allows the user to request any number of ports for their application. It automatically arbitrates requests and dispatches responses to the corresponding ports.
-
-The following example creates a crossbar and 2 user ports:
-
-.. code-block:: python
-
- self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
- user_port0 = self.sata_crossbar.get_port()
- user_port1 = self.sata_crossbar.get_port()
-
-Striping
-========
-
-The striping module segments data so that data is stored on N different controllers (RAID0 equivalent).
-
-.. code-block:: python
-
- +----> controller0 (dw)
- port (N*dw) <----+----> controllerX (dw)
- +----> controllerN (dw)
-
-Characteristics:
- - :code:`port`'s visible capacity = N x :code:`controller`'s visible capacity
- - :code:`port`'s throughput = N x (slowest) :code:`controller`'s throughput
-
-It can be used to increase capacity and writes/reads speed.
-
-The following example creates a striping with 2 HDDs:
-
-.. code-block:: python
-
- self.submodules.sata_striping = LiteSATAStriping([self.sata_core0, self.sata_core1])
-
-:code:`sata_striping`'s Sink and Source are the user interface.
-
-Mirroring
-=========
-
-The mirroring module handles N controllers and provides N ports (RAID1 equivalent).
-
-Each port has its dedicated controller for reads:
-
-.. code-block:: python
-
- port0 <----> controller0
- portX <----> controllerX
- portN <----> controllerN
-
-Writes are mirrored on each controller:
-
-.. code-block:: python
-
- (port0 write) | (portN write)
- port0 ----------+----> controller0 | port0 (stalled) +-----> controller0
- portX (stalled) +----> controllerX | portX (stalled) +-----> controllerX
- portN (stalled) +----> controllerN | portN ----------+-----> controllerN
-
-Writes have priority on reads. When a write is presented on one of the ports, the module waits for all ongoing reads to finish and commute to write mode. Once all writes are serviced it returns to read mode.
-
-Characteristics:
- - :code:`port`'s visible capacity = :code:`controller`'s visible capacity
- - total writes throughput = (slowest) :code:`controller`'s throughput
- - total reads throughput = N x :code:`controller`'s throughput
-
-It can be used for data redundancy and/or to increase the total read speed.
-
-The following example creates a mirroring with 2 HDDs:
-
-.. code-block:: python
-
- self.submodules.sata_mirroring = LiteSATAMirroring([self.sata_core0, self.sata_core1])
-
-:code:`sata_striping`'s :code:`ports[0]` and :code:`ports[1]` are the user interfaces.
-
-Module combinations
-===================
-
-Since all frontend modules share the same interface, it's easy to combine them together.
-
-In the following code, we have 4 HDDs, do a striping with (0,1) and (2,3), a mirroring on top of that and then create a crossbar on the first port of our mirroring module:
-
-.. code-block:: python
-
- self.submodules.sata_striping0 = LiteSATAStriping([self.sata_core0, self.sata_core1])
- self.submodules.sata_striping1 = LiteSATAStriping([self.sata_core2, self.sata_core3])
- self.submodules.sata_mirroring = LiteSATAMirroring([self.sata_striping0, self.sata_striping1])
- self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_mirroring.ports[0])
- self.user_port0 = self.sata_crossbar.get_port()
- self.user_port1 = self.sata_crossbar.get_port()
-
-This code provides the following user interfaces: :code:`self.user_port0`, :code:`self.user_port1` and :code:`self.sata_mirroring.ports[1]`.
-
-
-Examples
-========
-
-Since it's probably easier to figure out how to use the frontend modules with real use cases, we provides example designs:
-
-- A BIST_ (Data generator and checker) design that can be used to understand how to connect your logic to the user_port provided by the crossbar.
-
-- A Striping_ design that can be used to understand how to combine 4 HDDs together in striping mode and do a BIST on it.
-
-- A Mirroring_ design that can be used to understand how to combine 4 HDDs together in mirroring mode and do a BIST on it.
-
-.. _BIST: https://github.com/m-labs/misoc/blob/master/misoclib/mem/litesata/example_designs/targets/bist.py
-
-.. _Striping: https://github.com/m-labs/misoc/blob/master/misoclib/mem/litesata/example_designs/targets/striping.py
-
-.. _Mirroring: https://github.com/m-labs/misoc/blob/master/misoclib/mem/litesata/example_designs/targets/mirroring.py
+++ /dev/null
-.. _FAQ:
-
-===
-FAQ
-===
-.. note::
- Please contribute to this document.
+++ /dev/null
-.. _bug-reports:
-
-=============
-Bug Reporting
-=============
-- send us feedback and suggestions for improvements
-- send us bug reports when something goes wrong
-- send us the modifications and improvements you have done to LiteSATA.
- The use of "git format-patch" is recommended. If your submission is large and
- complex and/or you are not sure how to proceed, feel free to discuss it with us.
+++ /dev/null
-.. _sdk-download-and-install:
-
-=========================
-Download and installation
-=========================
-Please follow the "Getting started" section of the LiteSATA README_.
-
-.. _README: https://github.com/m-labs/misoc/blob/master/misoclib/mem/litesata/README
+++ /dev/null
-.. _getting-started-index:
-
-===============
-Getting Started
-===============
-
-Now that you know why LiteSATA is the :ref:`core for you <about>`, it's time to *get started*.
-
-This section explains the procedure for downloading and installing the tools.
-
-.. toctree::
- :maxdepth: 1
-
- downloads
- FAQ
- bug_reports
+++ /dev/null
-.. _about:
-
-==============
-About LiteSATA
-==============
-
-LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
-
-LiteSATA is part of the MiSoC libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in modern SoCs such as Ethernet, SATA, PCIe, SDRAM controller...
-
-The core uses simple and specific streaming buses and will provide in the future
-adapters to use standardized AXI or Avalon-ST streaming buses.
-
-Since Python is used to describe the gateware, the core is highly and easily
-configurable.
-
-The synthetizable BIST can be used as a starting point to integrate SATA in
-your own SoC.
-
-LiteSATA uses technologies developed in partnership with M-Labs Ltd:
- - Migen enables generating HDL with Python in an efficient way.
- - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
-
-LiteSATA can be used as a Python library or can be integrated with your standard
-design flow by generating the Verilog RTL that you will use as a standard core.
-
-.. _about-toolchain:
-
-Features
-========
-PHY:
- - OOB, COMWAKE, COMINIT
- - ALIGN inserter/remover and bytes alignment on K28.5
- - 8B/10B encoding/decoding in transceiver
- - Errors detection and reporting
- - 32 bits interface
- - 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)
-Core:
- Link:
- - CONT inserter/remover
- - Scrambling/Descrambling of data
- - CRC inserter/checker
- - HOLD insertion/detection
- - Errors detection and reporting
- Transport/Command:
- - Easy to use user interfaces (Can be used with or without CPU)
- - 48 bits sector addressing
- - 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE
- - Errors detection and reporting
-
-Frontend:
- - Configurable crossbar (simply declare your crossbar and use core.crossbar.get_port() to add a new port!)
- - Ports arbitration transparent to the user
- - Synthesizable BIST
- - Striping module to segment data on multiple HDDs and increase write/read speed and capacity. (RAID0 equivalent)
- - Mirroring module for data redundancy and increase read speeds. (RAID1 equivalent)
-
-
-Possibles improvements
-======================
-- add standardized interfaces (AXI, Avalon-ST)
-- add NCQ support
-- add AES hardware encryption
-- add on-the-flow compression/decompression
-- add support for Altera PHYs.
-- add support for Lattice PHYs.
-- add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are
- supported)
-- add Zynq Linux drivers.
-- ... See below Support and Consulting :)
-
-Support and Consulting
-======================
-We love open-source hardware and like sharing our designs with others.
-
-LiteSATA is developed and maintained by EnjoyDigital.
-
-If you would like to know more about LiteSATA or if you are already a happy user
-and would like to extend it for your needs, EnjoyDigital can provide standard
-commercial support as well as consulting services.
-
-So feel free to contact us, we'd love to work with you! (and eventually shorten
-the list of the possible improvements :)
-
-Contact
-=======
-E-mail: florent [AT] enjoy-digital.fr
+++ /dev/null
-.. _community:
-
-=========
-Community
-=========
+++ /dev/null
-.. _intro-index:
-
-======================
-Introducing LiteSATA
-======================
-
-This section explains what LiteSATA does, why it is needed, its limitations and its licensing. After reading, you will understand whether LiteSATA is the right core for you, and where to go if you have :ref:`further questions <community>`.
-
-.. toctree::
- :maxdepth: 1
-
- about
- license
- release_notes
- talks_and_publications
+++ /dev/null
-.. _license:
-
-===================
-Open Source License
-===================
-
-LiteSATA is released under the very permissive two-clause BSD license. Under the
-terms of this license, you are authorized to use LiteSATA for closed-source
-proprietary designs.
-Even though we do not require you to do so, those things are awesome, so please
-do them if possible:
-
- - tell us that you are using LiteSATA
- - cite LiteSATA in publications related to research it has helped
- - send us feedback and suggestions for improvements
- - send us bug reports when something goes wrong
- - send us the modifications and improvements you have done to LiteSATA.
-
-::
-
- Unless otherwise noted, LiteSATA is copyright (C) 2014-2015 HKU.
-
- Redistribution and use in source and binary forms, with or without modification,
- are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-
- Other authors retain ownership of their contributions. If a submission can
- reasonably be considered independently copyrightable, it's yours and we
- encourage you to claim it with appropriate copyright notices. This submission
- then falls under the "otherwise noted" category. All submissions are strongly
- encouraged to use the two-clause BSD license reproduced above.
+++ /dev/null
-.. _release-notes:
-
-=============
-Release Notes
-=============
-
-.. _ChangeLog:
-
-ChangeLog
-=========
-0.9.0:
- - First release supporting Xilinx Kintex7.
+++ /dev/null
-.. _talks-and-publications:
-
-======================
-Talks and Publications
-======================
-
- - Migen / MiSoC documentation:
- - `User guide <http://m-labs.hk/migen.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
- - `Tutorial: An introduction to Migen <http://m-labs.hk/migen-tutorial.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
-
- - Migen / MiSoC presentations:
- - `Lecture slides <http://m-labs.hk/migen-slides.pdf>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
- - `EHSM 2012 presentation <https://www.youtube.com/watch?v=yxKMsAi_WEA>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
- - `ORCONF2014 <https://www.youtube.com/watch?v=AfEPbw4nREo>`_ (`fallen <https://github.com/fallen>`_)
+++ /dev/null
-.. _phy-index:
-
-===
-PHY
-===
-.. note::
- Please contribute to this document, or support us financially to write it.
\ No newline at end of file
+++ /dev/null
-.. _simulation-index:
-
-==========
-Simulation
-==========
-
-.. note::
- Please contribute to this document, or support us financially to write it.
-
-Simulations are available in ./test:
-
- - :code:`crc_tb`
- - :code:`scrambler_tb`
- - :code:`phy_datapath_tb`
- - :code:`link_tb`
- - :code:`command_tb`
- - :code:`bist_tb`
- - :code:`striping_tb`
- - :code:`mirroring_tb`
-
-Models for all the layers of SATA and a simplified HDD model are provided.
-To run a simulation, go to ./test and run:
-
- - :code:`make <simulation_name>`
+++ /dev/null
-.. _sata-index:
-
-========================
-SATA Specification
-========================
-
-.. note::
- This chapter is a lightly modified version of the excellent SATA summary found in Chapter 2 of Erik Landström's Thesis_.
-
-Serial Advanced Technology Attachment (SATA) is a serial link replacement of
-Parallel ATA (PATA), both standards for communication with mass storage devices.
-This high-speed serial link is a differential layer that utilizes Gigabit technology
-and 8b/10b encoding. The link supports full duplex but the protocol only permits frames
-in one direction at a time. The other non-data direction is used for flow control of the
-data stream
-
-.. figure:: sata_layers.png
- :scale: 50 %
- :align: center
-
- SATA layers.
-
-SATA's architecture consists of four layers, Application, Transport, Link, and Physical.
-The Application layer is responsible for overall ATA commands and of controlling SATA
-register accesses. The transport layer places control information and data to be transferred between
-the host and corresponding SATA device in a data packets. One such packet is called a frame
-information structure (FIS). The Link layer is responsible for taking data from a FIS and
-encode/decode it using 8b/10b. It also inserts control characters for flow control and calculates
-the cyclic redundancy check (CRC) for error detection. Finally the Phy layer’s task is to deliver
-and receive the encoded serial data stream on the wire.
-
-Dword - Data Representation
-===========================
-In the SATA standard the smallest allowed data is a Dword, its 32 bits are divided
-into four bytes. Where each pair of bytes represent a word and a pair of words
-represent a Dword. In this way it’s easy to see that odd number of bytes is not
-allowed in SATA communication.
-
-.. figure:: byte_word_dword.png
- :scale: 50 %
- :align: center
-
- Byte, Word, Dword definitions.
-
-The Dwords can be represented by either a data Dword or a so called primitive. A
-primitive is a predefined Dword like for example start of frame (SOF) and end
-of frame (EOF).
-
-Primitives
-==========
-Primitives are Dwords with a purpose to enable and control the serial communication.
-They all begin with a control character followed by three other characters to
-fill up the Dword. The control character makes it easy to recognize a primitive from
-a ordinary Dword of a frame. There is 18 different primitives, all with a dedicated
-task like for example mark a frame with a SOF or to provide synchronization
-with the SYNC.
-
-8b/10b - Encoding
-=================
-8b/10b encoding is rather common in high speed applications, it’s used to provide
-bounded disparity but still provide enough toggling to make clock recovery possible
-(synchronize internal clock with the data stream). The bounded disparity means
-that in a string of twenty bits the difference between zeros and ones shall be -2, 0,
-or 2 and with a maximum runlength of five. The drawback is the created overhead
-of two bits per byte making the actual transfer speed of for example 1.5 Gbps link
-to 1.2 Gbps, a loss of 20 %. Since the 8b/10b extends the possible alphabet from
-256 symbols to 1024 it can provide detection and encoding of special characters
-(also called k-characters) in an easy and effective way. This is used in the SATA
-standard by encoding every primitive as such special characters.
-
-
-Out of Band Signaling
-======================
-Since SATA devices and hosts always sends junk over its differential channels,
-when it is idle (otherwise the link is considered lost), there has to be a way of
-recognizing a signal before a link has been initialized. For this SATA uses so
-called out of band signaling (OOB) to initialize a connection between a host and a
-device. The OOB mechanism supports low speed transmission over a high speed
-connection, such as a SATA link. The OOB signals are non-differential but are sent
-over a differential channel. This is possible by letting the differential transmitters
-drive their output pins to the same voltage, resulting in a reduced difference and
-when a preset threshold limit is reached the receiver can recognize the signal as
-OOB.
-
-.. figure:: oob_signals.png
- :scale: 50 %
- :align: center
-
- OOB signals.
-
-As can be seen in the figure there are three types of (actually two
-since COMINIT and COMRESET are equal) valid OOB signals where bursts of
-six ALIGN are sent with different timing. The importance in the signaling lies
-in the timing, it does not really matter if an ALIGN or something else are sent
-because the receiver only detects the drop of voltage difference between rx+ and
-rx-. In the next figure the complete startup sequence is visualized and
-the calibration steps in it are optional to implement. The host sends COMRESET
-until the device is powered on and can respond with a COMINIT. Upon reception
-of the COMINIT the host sends a COMWAKE to the device which shall send a
-COMWAKE back. If this procedure is finished within a correct time the OOB signaling
-ends and the differential communication can proceed with determining the link speed
-(right part of the figure).
-
-.. figure:: oob_sequence.png
- :scale: 50 %
- :align: center
-
- OOB init sequence.
-
-Physical Layer
-==============
-This section describes the physical interface towards the actual SATA link.
-The features of the phy can be summarized to:
-
- - Transmit/Receive a 1.5 Gbps, 3.0 or 6.0 Gbps differential signal
- - Speed negotiation
- - OOB detection and transmission
- - Serialize a 10, 20, or other width parallel data from the link layer
- - Extract data from the serial data stream
- - Parallelize the data stream and send it to the link layer
- - Handle spread spectrum clocking (SSC), a clock modulation technique used
- to reduce unintentional interference to radio signals
-
-At startup the physical layer is in its OOB state and after a link has been initiated
-it changes to Idle Bus condition and normal SATA communication is now
-supported. Since the SATA connection is noisy the physical layer detects a frame
-when it receives a SOF primitive and it will keep on listening to the incoming
-signal until an EOF primitive is received. Except from FIS the SATA traffic
-also consists of single primitives which all are easy for the PHY to recognize because
-of their starting control character.
-
-Link Layer
-==========
-This section describes the SATA link layer.
-The link layer’s major tasks are:
-
- - Flow control
- - Encapsulate FISes received from transport layer
- - CRC generation and CRC check
- - FIS scrambling and de-scrambling
- - 8b/10b encoding/decoding
-
-A FIS is framed between a SOF and a EOF creating the boundaries of a frame.
-The last Dword before a EOF is the CRC value for the FIS. The CRC is calculated
-by applying the 32-bits generator polynomial G(x) in Equation on every bit in
-every non-primitive Dword in a FIS and then summarize (modulo 2) all these terms
-together with the Initial Value. The CRC is fixed to value of 0x52325032.
-
-.. figure:: crc.png
- :scale: 50 %
- :align: center
-
- CRC polynom.
-
-Scrambling a FIS reduces EMI by spreading the noise over a broader frequency
-spectrum. The scrambling algorithm can be expressed as a polynomial or as a linear
-feedback shift register. The scrambling creates a pseudorandom bit pattern of the
-data that reduces EMI. The algorithm resets to a of value of 0xFFFF every time a SOF
-is encountered at the scrambler. The de-scrambler uses the same algorithm on scrambled
-data so it retakes its original form.
-
-.. figure:: scrambler.png
- :scale: 50 %
- :align: center
-
- Scrambler LFSR polynom.
-
-It is important that the CRC calculations are made at original data and that
-the scrambling/de-scrambling are made between the CRC and the 8b/10b encoding/decoding.
-The flow control between host and device is managed by sending
-primitives to one another telling its status (which originates from the transport
-layer). Some of these primitives can be inserted into FIS. Primitives are not
-supposed to be scrambled or added to the CRC sum. Internally the flow control
-are regulated by signaling between the layers.
-
-Transport Layer
-===============
-The main task for the SATA transport layer is to handle FISes and a brief description
-of the layer’s features follows:
-
- - Flow control
- - Error control
- - Error reporting
- - FIS construction
- - FIS decomposition
- - FIS buffering for retransmission
-
-There are eight types of FISes each with its specific 8-bit ID and unique header.
-FISes vary in size from 1 Dword up to 2049 Dwords. The number of bytes in a
-FIS are always a multiple of four so the transport layer has to fill up with zeros if
-there are bytes or bits missing for an entire Dword.
-The flow control in this case is only to report to the link layer that the data buffers
-are close to over- or underflow. Errors detected are supposed to be reported to
-the application layer and the detectable errors are:
-
- - Errors from lower layers like 8b/10b disparity error or CRC errors.
- - SATA state or protocol errors caused by standard violation.
- - Frame errors like malformed header.
- - Internal transport layer errors like buffer overflow.
-
-Errors are handled in different ways, for example are resending of complete FISes
-supported for all kind of FISes besides the data FISes (and the BIST FIS which
-is used typically during testing), because that would need buffers in size of 8192
-bytes (maximum supported FIS size). The max sized non-data FIS is 28 bytes so
-the costs of a large buffer can be spared.
-
-Command Layer
-=============
-The command layer tells the transport layer what kind of FISes to send and receive
-for each specific command and in which order those FISes are expexted to be delivered.
-
-.. note::
- This chapter is a lightly modified version of the excellent SATA summary found in Chapter 2 of Erik Landström's Thesis_.
-
-.. _Thesis: http://www.diva-portal.org/smash/get/diva2:207798/FULLTEXT01.pdf
+++ /dev/null
-.. _test-index:
-
-====
-Test
-====
-
-.. note::
- Please contribute to this document, or support us financially to write it.
-
-A synthetizable BIST is provided and can be controlled with ./test/bist.py.
-By using LiteScope and the provided ./test/test_link.py example you are able to
-visualize the internal logic of the design and even inject the captured data into
-the HDD model!
+++ /dev/null
-<img alt="./_static/LiteSATA_logo_full.png" src="_static/LiteSATA_logo_full.png">
-
-<h3>LiteSATA provides a <b>small footprint and configurable FPGA SATA gen1/2 core</b>.</h3>
-
-<div class="container" style="width:100%;margin-bottom:10px;">
-
- <div class="one-third-container" style="width:32%; display:inline-block;">
- <div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
- <div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Small footprint</div>
- <div class="signpost-body" style=""><p>Thanks to simple and efficient Migen building blocks and the KISS principe used to develop this core, LiteSATA footprint is really small!</p></div>
- </div>
- </div>
- <div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
- <div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
- <div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Configurable</div>
- <div class="signpost-body" style=""><p>LiteSATA generates HDL using Migen, a Python-based logic design system. The core is easily configurable to fit
- user's needs! (number of crossbar ports, RAID configuration, included BIST and so on...)</p></div>
- </div>
- </div>
- <div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
- <div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px; margin-right:5px;">
- <div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Portable</div>
- <div class="signpost-body" style=""><p>Porting the core to another vendor or family only requires adapting or adding a new PHY. All others building blocks of the core are generic.</p></div>
- </div>
- </div>
-</div>
+++ /dev/null
-.. title:: Main
-
-.. _home-page:
-
-.. raw:: html
- :file: home_page_layout.html
-
-
------
-
-News
-====
-
-- First 0.9.0 release supporting Xilinx Kintex7.
-
-.. toctree::
- :hidden:
-
- docs/intro/index
- docs/getting_started/index
- docs/specification/index
- docs/phy/index
- docs/core/index
- docs/frontend/index
- docs/simulation/index
- docs/test/index
+++ /dev/null
-#!/usr/bin/env python3
-
-import sys
-import os
-import argparse
-import subprocess
-import struct
-import importlib
-
-from mibuild.tools import write_to_file
-from migen.util.misc import autotype
-from migen.fhdl import verilog, edif
-from migen.fhdl.structure import _Fragment
-from migen.bank.description import CSRStatus
-from mibuild import tools
-from mibuild.xilinx.common import *
-
-from misoclib.soc import cpuif
-from misoclib.mem.litesata.common import *
-
-
-def _import(default, name):
- return importlib.import_module(default + "." + name)
-
-
-def _get_args():
- parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
- description="""\
-LiteSATA - based on Migen.
-
-This program builds and/or loads LiteSATA components.
-One or several actions can be specified:
-
-clean delete previous build(s).
-build-rtl build verilog rtl.
-build-bitstream build-bitstream build FPGA bitstream.
-build-csr-csv save CSR map into CSV file.
-
-load-bitstream load bitstream into volatile storage.
-
-all clean, build-csr-csv, build-bitstream, load-bitstream.
-""")
-
- parser.add_argument("-t", "--target", default="bist", help="Core type to build")
- parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
- parser.add_argument("-p", "--platform", default=None, help="platform to build for")
- parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
- parser.add_argument("-Op", "--platform-option", default=[("programmer", "vivado")], nargs=2, action="append", help="set platform-specific option")
- parser.add_argument("-Ob", "--build-option", default=[], nargs=2, action="append", help="set build option")
- parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")
-
- parser.add_argument("action", nargs="+", help="specify an action")
-
- return parser.parse_args()
-
-# Note: misoclib need to be installed as a python library
-
-if __name__ == "__main__":
- args = _get_args()
-
- # create top-level Core object
- target_module = _import("targets", args.target)
- if args.sub_target:
- top_class = getattr(target_module, args.sub_target)
- else:
- top_class = target_module.default_subtarget
-
- if args.platform is None:
- platform_name = top_class.default_platform
- else:
- platform_name = args.platform
- platform_module = _import("platforms", platform_name)
- platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
- platform = platform_module.Platform(**platform_kwargs)
-
- build_name = top_class.__name__.lower() + "-" + platform_name
- top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
- soc = top_class(platform, **top_kwargs)
- soc.finalize()
- try:
- memory_regions = soc.get_memory_regions()
- csr_regions = soc.get_csr_regions()
- except:
- pass
-
- # decode actions
- action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
- actions = {k: False for k in action_list}
- for action in args.action:
- if action in actions:
- actions[action] = True
- else:
- print("Unknown action: "+action+". Valid actions are:")
- for a in action_list:
- print(" "+a)
- sys.exit(1)
-
- try:
- revision = soc.sata_phy.revision
- except:
- revision = soc.sata_phy0.revision
-
- print("""
- __ _ __ _______ _________
- / / (_) /____ / __/ _ /_ __/ _ |
- / /__/ / __/ -_)\ \/ __ |/ / / __ |
- /____/_/\__/\__/___/_/ |_/_/ /_/ |_|
-
-A small footprint and configurable SATA core
- powered by Migen
-
-====== Building options: ======
-{} / {} Gbps
-System Clk: {} MHz (min: {} MHz)
-===============================""".format(
- revision.replace("sata_", "SATA "), bitrates[revision],
- soc.clk_freq/1000000, frequencies[revision]
- )
-)
-
- # dependencies
- if actions["all"]:
- actions["build-csr-csv"] = True
- actions["build-bitstream"] = True
- actions["load-bitstream"] = True
-
- if actions["build-bitstream"]:
- actions["build-csr-csv"] = True
- actions["build-bitstream"] = True
- actions["load-bitstream"] = True
-
- if actions["clean"]:
- subprocess.call(["rm", "-rf", "build/*"])
-
- if actions["build-csr-csv"]:
- csr_csv = cpuif.get_csr_csv(csr_regions)
- write_to_file(args.csr_csv, csr_csv)
-
- if actions["build-core"]:
- ios = soc.get_ios()
- if not isinstance(soc, _Fragment):
- soc = soc.get_fragment()
- platform.finalize(soc)
- so = {
- NoRetiming: XilinxNoRetiming,
- MultiReg: XilinxMultiReg,
- AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
- }
- v_output = verilog.convert(soc, ios, special_overrides=so)
- v_output.write("build/litesata.v")
-
- if actions["build-bitstream"]:
- build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
- vns = platform.build(soc, build_name=build_name, **build_kwargs)
- if hasattr(soc, "do_exit") and vns is not None:
- if hasattr(soc.do_exit, '__call__'):
- soc.do_exit(vns)
-
- if actions["load-bitstream"]:
- prog = platform.create_programmer()
- prog.load_bitstream("build/" + build_name + platform.bitstream_ext)
+++ /dev/null
-from mibuild.generic_platform import *
-from mibuild.platforms import kc705
-
-_sata_io = [
- ("sata_clocks", 0,
- Subsignal("refclk_p", Pins("HPC:GBTCLK0_M2C_P")),
- Subsignal("refclk_n", Pins("HPC:GBTCLK0_M2C_N"))
- ),
- ("sata", 0,
- Subsignal("txp", Pins("HPC:DP0_C2M_P")),
- Subsignal("txn", Pins("HPC:DP0_C2M_N")),
- Subsignal("rxp", Pins("HPC:DP0_M2C_P")),
- Subsignal("rxn", Pins("HPC:DP0_M2C_N"))
- ),
- ("sata", 1,
- Subsignal("txp", Pins("HPC:DP1_C2M_P")),
- Subsignal("txn", Pins("HPC:DP1_C2M_N")),
- Subsignal("rxp", Pins("HPC:DP1_M2C_P")),
- Subsignal("rxn", Pins("HPC:DP1_M2C_N"))
- ),
- ("sata", 2,
- Subsignal("txp", Pins("HPC:DP2_C2M_P")),
- Subsignal("txn", Pins("HPC:DP2_C2M_N")),
- Subsignal("rxp", Pins("HPC:DP2_M2C_P")),
- Subsignal("rxn", Pins("HPC:DP2_M2C_N"))
- ),
- ("sata", 3,
- Subsignal("txp", Pins("HPC:DP3_C2M_P")),
- Subsignal("txn", Pins("HPC:DP3_C2M_N")),
- Subsignal("rxp", Pins("HPC:DP3_M2C_P")),
- Subsignal("rxn", Pins("HPC:DP3_M2C_N"))
- )
-]
-
-
-class Platform(kc705.Platform):
- def __init__(self, *args, **kwargs):
- kc705.Platform.__init__(self, *args, **kwargs)
- self.add_extension(_sata_io)
-
- def do_finalize(self, fragment):
- try:
- self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
- except ConstraintError:
- pass
- try:
- self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
- except ConstraintError:
- pass
- self.add_platform_command("""
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 2.5 [current_design]
-""")
+++ /dev/null
-from mibuild.generic_platform import *
-from mibuild.xilinx.platform import XilinxPlatform
-
-_io = [
- ("sys_clk", 0, Pins("X")),
- ("sys_rst", 1, Pins("X")),
- ("sata_clocks", 0,
- Subsignal("refclk_p", Pins("X")),
- Subsignal("refclk_n", Pins("X")),
- ),
- ("sata", 0,
- Subsignal("txp", Pins("X")),
- Subsignal("txn", Pins("X")),
- Subsignal("rxp", Pins("X")),
- Subsignal("rxn", Pins("X")),
- ),
-]
-
-
-class Platform(XilinxPlatform):
- def __init__(self, device="xc7k325t", programmer=""):
- XilinxPlatform.__init__(self, device, _io)
-
- def do_finalize(self, *args, **kwargs):
- pass
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from migen.genlib.cdc import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-
-from misoclib.soc import SoC
-
-from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.frontend.la import LiteScopeLA
-from misoclib.tools.litescope.core.port import LiteScopeTerm
-
-from misoclib.com.uart.bridge import UARTWishboneBridge
-
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.phy import LiteSATAPHY
-from misoclib.mem.litesata.core import LiteSATACore
-from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
-from misoclib.mem.litesata.frontend.bist import LiteSATABIST
-
-
-class CRG(Module):
- def __init__(self, platform):
- self.clock_domains.cd_sys = ClockDomain()
-
- clk200 = platform.request("clk200")
- clk200_se = Signal()
- self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
-
- pll_locked = Signal()
- pll_fb = Signal()
- pll_sys = Signal()
- self.specials += [
- Instance("PLLE2_BASE",
- p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
-
- # VCO @ 1GHz
- p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
- p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
- i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
-
- # 200MHz
- p_CLKOUT0_DIVIDE=5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
-
- p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
-
- p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
-
- p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
-
- p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
- ),
- Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
- AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset")),
- ]
-
-
-class StatusLeds(Module):
- def __init__(self, platform, sata_phys):
- if not isinstance(sata_phys, list):
- sata_phys = [sata_phys]
- use_cd_num = False
- else:
- use_cd_num = True
- for i, sata_phy in enumerate(sata_phys):
- # 1Hz blinking leds (sata_rx and sata_tx clocks)
- rx_led = platform.request("user_led", 2*i)
-
- rx_cnt = Signal(32)
-
- freq = int(frequencies[sata_phy.revision]*1000*1000)
-
- rx_sync = getattr(self.sync, "sata_rx{}".format(str(i) if use_cd_num else ""))
- rx_sync += \
- If(rx_cnt == 0,
- rx_led.eq(~rx_led),
- rx_cnt.eq(freq//2)
- ).Else(
- rx_cnt.eq(rx_cnt-1)
- )
-
- # ready leds
- self.comb += platform.request("user_led", 2*i+1).eq(sata_phy.ctrl.ready)
-
-
-class BISTSoC(SoC):
- default_platform = "kc705"
- csr_map = {
- "sata_bist": 16
- }
- csr_map.update(SoC.csr_map)
- def __init__(self, platform):
- clk_freq = 200*1000000
- SoC.__init__(self, platform, clk_freq,
- cpu_type="none",
- with_csr=True, csr_data_width=32,
- with_uart=False,
- with_identifier=True,
- with_timer=False
- )
- self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
- self.add_wb_master(self.cpu_or_bridge.wishbone)
- self.submodules.crg = CRG(platform)
-
- # SATA PHY/Core/Frontend
- self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen3", clk_freq)
- self.submodules.sata_core = LiteSATACore(self.sata_phy)
- self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
- self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)
-
- # Status Leds
- self.submodules.leds = StatusLeds(platform, self.sata_phy)
-
- platform.add_platform_command("""
-create_clock -name sys_clk -period 5 [get_nets sys_clk]
-
-create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]
-create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk]
-
-set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
-set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
-set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
-set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
-""")
-
-class BISTSoCDevel(BISTSoC):
- csr_map = {
- "la": 17
- }
- csr_map.update(BISTSoC.csr_map)
- def __init__(self, platform):
- BISTSoC.__init__(self, platform)
-
- self.sata_core_link_rx_fsm_state = Signal(4)
- self.sata_core_link_tx_fsm_state = Signal(4)
- self.sata_core_transport_rx_fsm_state = Signal(4)
- self.sata_core_transport_tx_fsm_state = Signal(4)
- self.sata_core_command_rx_fsm_state = Signal(4)
- self.sata_core_command_tx_fsm_state = Signal(4)
-
- debug = (
- self.sata_phy.ctrl.ready,
-
- self.sata_phy.source.stb,
- self.sata_phy.source.data,
- self.sata_phy.source.charisk,
-
- self.sata_phy.sink.stb,
- self.sata_phy.sink.data,
- self.sata_phy.sink.charisk,
-
- self.sata.core.command.sink.stb,
- self.sata.core.command.sink.sop,
- self.sata.core.command.sink.eop,
- self.sata.core.command.sink.ack,
- self.sata.core.command.sink.write,
- self.sata.core.command.sink.read,
- self.sata.core.command.sink.identify,
-
- self.sata.core.command.source.stb,
- self.sata.core.command.source.sop,
- self.sata.core.command.source.eop,
- self.sata.core.command.source.ack,
- self.sata.core.command.source.write,
- self.sata.core.command.source.read,
- self.sata.core.command.source.identify,
- self.sata.core.command.source.failed,
- self.sata.core.command.source.data,
-
- self.sata_core_link_rx_fsm_state,
- self.sata_core_link_tx_fsm_state,
- self.sata_core_transport_rx_fsm_state,
- self.sata_core_transport_tx_fsm_state,
- self.sata_core_command_rx_fsm_state,
- self.sata_core_command_tx_fsm_state,
- )
-
- self.submodules.la = LiteScopeLA(debug, 2048)
- self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
-
- def do_finalize(self):
- BISTSoC.do_finalize(self)
- self.comb += [
- self.sata_core_link_rx_fsm_state.eq(self.sata.core.link.rx.fsm.state),
- self.sata_core_link_tx_fsm_state.eq(self.sata.core.link.tx.fsm.state),
- self.sata_core_transport_rx_fsm_state.eq(self.sata.core.transport.rx.fsm.state),
- self.sata_core_transport_tx_fsm_state.eq(self.sata.core.transport.tx.fsm.state),
- self.sata_core_command_rx_fsm_state.eq(self.sata.core.command.rx.fsm.state),
- self.sata_core_command_tx_fsm_state.eq(self.sata.core.command.tx.fsm.state)
- ]
-
- def do_exit(self, vns):
- self.la.export(vns, "test/la.csv")
-
-default_subtarget = BISTSoC
+++ /dev/null
-from migen.genlib.resetsync import AsyncResetSynchronizer
-
-from targets import *
-
-from misoclib.soc import SoC
-
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.phy import LiteSATAPHY
-from misoclib.mem.litesata.core import LiteSATACore
-from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
-from misoclib.mem.litesata.frontend.bist import LiteSATABIST
-
-
-class Core(Module):
- default_platform = "verilog_backend"
- def __init__(self, platform, clk_freq=166*1000000, with_bist=True, nports=4):
- self.clk_freq = clk_freq
-
- # SATA PHY/Core/Frontend
- self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata"), "sata_gen2", clk_freq)
- self.submodules.sata_core = LiteSATACore(self.sata_phy)
- self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
-
- # BIST
- if with_bist:
- self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar)
-
- # Get user ports from crossbar
- self.user_ports = self.sata_crossbar.get_ports(nports)
-
- def get_ios(self):
- ios = set()
-
- # Transceiver
- for e in dir(self.sata_phy.clock_pads):
- obj = getattr(self.sata_phy.clock_pads, e)
- if isinstance(obj, Signal):
- ios = ios.union({obj})
- for e in dir(self.sata_phy.pads):
- obj = getattr(self.sata_phy.pads, e)
- if isinstance(obj, Signal):
- ios = ios.union({obj})
-
- # Status
- ios = ios.union({
- self.sata_phy.crg.ready,
- self.sata_phy.ctrl.ready
- })
-
- # BIST
- if hasattr(self, "sata_bist"):
- for bist_unit in ["generator", "checker"]:
- for signal in ["start", "sector", "count", "random", "done", "aborted", "errors"]:
- ios = ios.union({getattr(getattr(self.sata_bist, bist_unit), signal)})
- ios = ios.union({
- self.sata_bist.identify.start,
- self.sata_bist.identify.done,
- self.sata_bist.identify.source.stb,
- self.sata_bist.identify.source.data,
- self.sata_bist.identify.source.ack
- })
-
- # User ports
- def _iter_layout(layout):
- for e in layout:
- if isinstance(e[1], list):
- yield from _iter_layout(e[1])
- else:
- yield e
-
- for port in self.user_ports:
- for endpoint in [port.sink, port.source]:
- for e in _iter_layout(endpoint.layout):
- obj = getattr(endpoint, e[0])
- ios = ios.union({obj})
- return ios
-
-default_subtarget = Core
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from migen.genlib.cdc import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-
-from misoclib.soc import SoC
-
-from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.frontend.la import LiteScopeLA
-from misoclib.tools.litescope.core.port import LiteScopeTerm
-
-from misoclib.com.uart.bridge import UARTWishboneBridge
-
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.phy import LiteSATAPHY
-from misoclib.mem.litesata.core import LiteSATACore
-from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
-from misoclib.mem.litesata.frontend.mirroring import LiteSATAMirroring
-from misoclib.mem.litesata.frontend.bist import LiteSATABIST
-
-from misoclib.mem.litesata.example_designs.targets.bist import CRG, StatusLeds
-
-
-class MirroringSoC(SoC):
- default_platform = "kc705"
- csr_map = {
- "sata_bist0": 16,
- "sata_bist1": 17,
- "sata_bist2": 18,
- "sata_bist3": 19,
- }
- csr_map.update(SoC.csr_map)
- def __init__(self, platform):
- clk_freq = 200*1000000
- SoC.__init__(self, platform, clk_freq,
- cpu_type="none",
- with_csr=True, csr_data_width=32,
- with_uart=False,
- with_identifier=True,
- with_timer=False
- )
- self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
- self.add_wb_master(self.cpu_or_bridge.wishbone)
- self.submodules.crg = CRG(platform)
-
- # SATA PHYs
- sata_phy0 = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen3", clk_freq)
- sata_phy1 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 1), "sata_gen3", clk_freq)
- sata_phy2 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 2), "sata_gen3", clk_freq)
- sata_phy3 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 3), "sata_gen3", clk_freq)
- sata_phys = [sata_phy0, sata_phy1, sata_phy2, sata_phy3]
- for i, sata_phy in enumerate(sata_phys):
- sata_phy = RenameClockDomains(sata_phy, {"sata_rx": "sata_rx{}".format(str(i)),
- "sata_tx": "sata_tx{}".format(str(i))})
- setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)
-
- # SATA Cores
- self.submodules.sata_core0 = LiteSATACore(self.sata_phy0)
- self.submodules.sata_core1 = LiteSATACore(self.sata_phy1)
- self.submodules.sata_core2 = LiteSATACore(self.sata_phy2)
- self.submodules.sata_core3 = LiteSATACore(self.sata_phy3)
- sata_cores = [self.sata_core0, self.sata_core1, self.sata_core2, self.sata_core3]
-
- # SATA Frontend
- self.submodules.sata_mirroring = LiteSATAMirroring(sata_cores)
- self.submodules.sata_crossbar0 = LiteSATACrossbar(self.sata_mirroring.ports[0])
- self.submodules.sata_crossbar1 = LiteSATACrossbar(self.sata_mirroring.ports[1])
- self.submodules.sata_crossbar2 = LiteSATACrossbar(self.sata_mirroring.ports[2])
- self.submodules.sata_crossbar3 = LiteSATACrossbar(self.sata_mirroring.ports[3])
-
- # SATA Application
- self.submodules.sata_bist0 = LiteSATABIST(self.sata_crossbar0, with_csr=True)
- self.submodules.sata_bist1 = LiteSATABIST(self.sata_crossbar1, with_csr=True)
- self.submodules.sata_bist2 = LiteSATABIST(self.sata_crossbar2, with_csr=True)
- self.submodules.sata_bist3 = LiteSATABIST(self.sata_crossbar3, with_csr=True)
-
- # Status Leds
- self.submodules.status_leds = StatusLeds(platform, sata_phys)
-
-
- platform.add_platform_command("""
-create_clock -name sys_clk -period 5 [get_nets sys_clk]
-""")
-
- for i in range(len(sata_phys)):
- platform.add_platform_command("""
-create_clock -name {sata_rx_clk} -period 3.33 [get_nets {sata_rx_clk}]
-create_clock -name {sata_tx_clk} -period 3.33 [get_nets {sata_tx_clk}]
-
-set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}]
-set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}]
-set_false_path -from [get_clocks {sata_rx_clk}] -to [get_clocks sys_clk]
-set_false_path -from [get_clocks {sata_tx_clk}] -to [get_clocks sys_clk]
-""".format(sata_rx_clk="sata_rx{}_clk".format(str(i)),
- sata_tx_clk="sata_tx{}_clk".format(str(i))))
-
-
-default_subtarget = MirroringSoC
\ No newline at end of file
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from migen.genlib.cdc import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-
-from misoclib.soc import SoC
-
-from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.frontend.la import LiteScopeLA
-from misoclib.tools.litescope.core.port import LiteScopeTerm
-
-from misoclib.com.uart.bridge import UARTWishboneBridge
-
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.phy import LiteSATAPHY
-from misoclib.mem.litesata.core import LiteSATACore
-from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
-from misoclib.mem.litesata.frontend.striping import LiteSATAStriping
-from misoclib.mem.litesata.frontend.bist import LiteSATABIST
-
-from misoclib.mem.litesata.example_designs.targets.bist import CRG, StatusLeds
-
-
-class StripingSoC(SoC):
- default_platform = "kc705"
- csr_map = {
- "sata_bist": 16
- }
- csr_map.update(SoC.csr_map)
- def __init__(self, platform):
- clk_freq = 200*1000000
- SoC.__init__(self, platform, clk_freq,
- cpu_type="none",
- with_csr=True, csr_data_width=32,
- with_uart=False,
- with_identifier=True,
- with_timer=False
- )
- self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
- self.add_wb_master(self.cpu_or_bridge.wishbone)
- self.submodules.crg = CRG(platform)
-
- # SATA PHYs
- sata_phy0 = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen3", clk_freq)
- sata_phy1 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 1), "sata_gen3", clk_freq)
- sata_phy2 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 2), "sata_gen3", clk_freq)
- sata_phy3 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 3), "sata_gen3", clk_freq)
- sata_phys = [sata_phy0, sata_phy1, sata_phy2, sata_phy3]
- for i, sata_phy in enumerate(sata_phys):
- sata_phy = RenameClockDomains(sata_phy, {"sata_rx": "sata_rx{}".format(str(i)),
- "sata_tx": "sata_tx{}".format(str(i))})
- setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)
-
- # SATA Cores
- self.submodules.sata_core0 = LiteSATACore(self.sata_phy0)
- self.submodules.sata_core1 = LiteSATACore(self.sata_phy1)
- self.submodules.sata_core2 = LiteSATACore(self.sata_phy2)
- self.submodules.sata_core3 = LiteSATACore(self.sata_phy3)
- sata_cores = [self.sata_core0, self.sata_core1, self.sata_core2, self.sata_core3]
-
- # SATA Frontend
- self.submodules.sata_striping = LiteSATAStriping(sata_cores)
- self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_striping)
-
- # SATA Application
- self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)
-
- # Status Leds
- self.submodules.status_leds = StatusLeds(platform, sata_phys)
-
-
- platform.add_platform_command("""
-create_clock -name sys_clk -period 5 [get_nets sys_clk]
-""")
-
- for i in range(len(sata_phys)):
- platform.add_platform_command("""
-create_clock -name {sata_rx_clk} -period 3.33 [get_nets {sata_rx_clk}]
-create_clock -name {sata_tx_clk} -period 3.33 [get_nets {sata_tx_clk}]
-
-set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}]
-set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}]
-set_false_path -from [get_clocks {sata_rx_clk}] -to [get_clocks sys_clk]
-set_false_path -from [get_clocks {sata_tx_clk}] -to [get_clocks sys_clk]
-""".format(sata_rx_clk="sata_rx{}_clk".format(str(i)),
- sata_tx_clk="sata_tx{}_clk".format(str(i))))
-
-
-class StripingSoCDevel(StripingSoC):
- csr_map = {
- "la": 17
- }
- csr_map.update(StripingSoC.csr_map)
- def __init__(self, platform):
- StripingSoC.__init__(self, platform)
-
- self.sata_core0_link_tx_fsm_state = Signal(4)
- self.sata_core0_link_rx_fsm_state = Signal(4)
-
- self.sata_core1_link_tx_fsm_state = Signal(4)
- self.sata_core1_link_rx_fsm_state = Signal(4)
-
- self.sata_core2_link_tx_fsm_state = Signal(4)
- self.sata_core2_link_rx_fsm_state = Signal(4)
-
- self.sata_core3_link_tx_fsm_state = Signal(4)
- self.sata_core3_link_rx_fsm_state = Signal(4)
-
- debug = (
- self.sata_phy0.ctrl.ready,
- self.sata_phy1.ctrl.ready,
- self.sata_phy2.ctrl.ready,
- self.sata_phy3.ctrl.ready,
-
- self.sata_core0_link_tx_fsm_state,
- self.sata_core0_link_rx_fsm_state,
-
- self.sata_core0.sink.stb,
- self.sata_core0.source.stb,
-
- self.sata_phy0.source.stb,
- self.sata_phy0.source.data,
- self.sata_phy0.source.charisk,
-
- self.sata_phy0.sink.stb,
- self.sata_phy0.sink.data,
- self.sata_phy0.sink.charisk,
-
- self.sata_core1_link_tx_fsm_state,
- self.sata_core1_link_rx_fsm_state,
-
- self.sata_core1.sink.stb,
- self.sata_core1.source.stb,
-
- self.sata_phy1.source.stb,
- self.sata_phy1.source.data,
- self.sata_phy1.source.charisk,
-
- self.sata_phy1.sink.stb,
- self.sata_phy1.sink.data,
- self.sata_phy1.sink.charisk,
-
- self.sata_core2_link_tx_fsm_state,
- self.sata_core2_link_rx_fsm_state,
-
- self.sata_core2.sink.stb,
- self.sata_core2.source.stb,
-
- self.sata_phy2.source.stb,
- self.sata_phy2.source.data,
- self.sata_phy2.source.charisk,
-
- self.sata_phy2.sink.stb,
- self.sata_phy2.sink.data,
- self.sata_phy2.sink.charisk,
-
- self.sata_core3_link_tx_fsm_state,
- self.sata_core3_link_rx_fsm_state,
-
- self.sata_core3.sink.stb,
- self.sata_core3.source.stb,
-
- self.sata_phy3.source.stb,
- self.sata_phy3.source.data,
- self.sata_phy3.source.charisk,
-
- self.sata_phy3.sink.stb,
- self.sata_phy3.sink.data,
- self.sata_phy3.sink.charisk
- )
-
- self.submodules.la = LiteScopeLA(debug, 2048)
- self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
-
- def do_finalize(self):
- StripingSoC.do_finalize(self)
- self.comb += [
- self.sata_core0_link_rx_fsm_state.eq(self.sata_core0.link.rx.fsm.state),
- self.sata_core0_link_tx_fsm_state.eq(self.sata_core0.link.tx.fsm.state),
- self.sata_core1_link_rx_fsm_state.eq(self.sata_core1.link.rx.fsm.state),
- self.sata_core1_link_tx_fsm_state.eq(self.sata_core1.link.tx.fsm.state),
- self.sata_core2_link_rx_fsm_state.eq(self.sata_core2.link.rx.fsm.state),
- self.sata_core2_link_tx_fsm_state.eq(self.sata_core2.link.tx.fsm.state),
- self.sata_core3_link_rx_fsm_state.eq(self.sata_core3.link.rx.fsm.state),
- self.sata_core3_link_tx_fsm_state.eq(self.sata_core3.link.tx.fsm.state),
- ]
-
- def do_exit(self, vns):
- self.la.export(vns, "test/la.csv")
-
-
-default_subtarget = StripingSoC
\ No newline at end of file
+++ /dev/null
-import time
-import argparse
-import random as rand
-from collections import OrderedDict
-from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver
-
-KB = 1024
-MB = 1024*KB
-GB = 1024*MB
-
-logical_sector_size = 512
-
-
-class Timer:
- def __init__(self):
- self.value = None
-
- def start(self):
- self._start = time.time()
-
- def stop(self):
- self._stop = time.time()
- self.value = max(self._stop - self._start, 1/1000000)
-
-
-class LiteSATABISTUnitDriver:
- def __init__(self, regs, name):
- self.regs = regs
- self.name = name
- self.frequency = regs.identifier_frequency.read()
- self.time = 0
- for s in ["start", "sector", "count", "loops", "random", "done", "aborted", "errors", "cycles"]:
- setattr(self, s, getattr(regs, name + "_" + s))
-
- def run(self, sector, count, loops, random, blocking=True, hw_timer=True):
- self.sector.write(sector)
- self.count.write(count)
- self.loops.write(loops)
- self.random.write(random)
- timer = Timer()
- timer.start()
- self.start.write(1)
- if blocking:
- while (self.done.read() == 0):
- pass
- timer.stop()
- aborted = self.aborted.read()
- if not aborted:
- if hw_timer:
- self.time = self.cycles.read()/self.frequency
- else:
- self.time = timer.value
- speed = (loops*count*logical_sector_size)/self.time
- errors = self.errors.read()
- else:
- speed = 0
- errors = -1
- return (aborted, errors, speed)
-
-
-class LiteSATABISTGeneratorDriver(LiteSATABISTUnitDriver):
- def __init__(self, regs, name):
- LiteSATABISTUnitDriver.__init__(self, regs, name + "_generator")
-
-
-class LiteSATABISTCheckerDriver(LiteSATABISTUnitDriver):
- def __init__(self, regs, name):
- LiteSATABISTUnitDriver.__init__(self, regs, name + "_checker")
-
-
-class LiteSATABISTIdentifyDriver:
- def __init__(self, regs, name):
- self.regs = regs
- self.name = name
- for s in ["start", "done", "data_width", "source_stb", "source_ack", "source_data"]:
- setattr(self, s, getattr(regs, name + "_identify_" + s))
- self.data = []
-
- def read_fifo(self):
- self.data = []
- while self.source_stb.read():
- dword = self.source_data.read()
- word_lsb = dword & 0xffff
- word_msb = (dword >> 16) & 0xffff
- self.data += [word_lsb, word_msb]
- self.source_ack.write(1)
-
- def run(self, blocking=True):
- self.read_fifo() # flush the fifo before we start
- self.start.write(1)
- if blocking:
- while (self.done.read() == 0):
- pass
- self.read_fifo()
- self.decode()
-
- def decode(self):
- self.serial_number = ""
- for i, word in enumerate(self.data[10:20]):
- s = word.to_bytes(2, byteorder='big').decode("utf-8")
- self.serial_number += s
- self.firmware_revision = ""
- for i, word in enumerate(self.data[23:27]):
- s = word.to_bytes(2, byteorder='big').decode("utf-8")
- self.firmware_revision += s
- self.model_number = ""
- for i, word in enumerate(self.data[27:46]):
- s = word.to_bytes(2, byteorder='big').decode("utf-8")
- self.model_number += s
-
- self.total_sectors = self.data[100]
- self.total_sectors += (self.data[101] << 16)
- self.total_sectors += (self.data[102] << 32)
- self.total_sectors += (self.data[103] << 48)
-
- self.capabilities = OrderedDict()
- self.capabilities["SATA Gen1"] = (self.data[76] >> 1) & 0x1
- self.capabilities["SATA Gen2"] = (self.data[76] >> 2) & 0x1
- self.capabilities["SATA Gen3"] = (self.data[76] >> 3) & 0x1
- self.capabilities["48 bits LBA supported"] = (self.data[83] >> 10) & 0x1
-
- def hdd_info(self):
- info = "Serial Number: " + self.serial_number + "\n"
- info += "Firmware Revision: " + self.firmware_revision + "\n"
- info += "Model Number: " + self.model_number + "\n"
- info += "Capacity: {:3.2f} GB\n".format((self.total_sectors*logical_sector_size)/GB)
- for k, v in self.capabilities.items():
- info += k + ": " + str(v) + "\n"
- print(info, end="")
-
-
-def _get_args():
- parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
- description="""\
-SATA BIST utility.
-""")
- parser.add_argument("--port", default=2, help="UART port")
- parser.add_argument("--baudrate", default=115200, help="UART baudrate")
- parser.add_argument("--busword", default=32, help="CSR busword")
- parser.add_argument("-s", "--transfer_size", default=1024, help="transfer sizes (in KB, up to 16MB)")
- parser.add_argument("-l", "--total_length", default=256, help="total transfer length (in MB, up to HDD capacity)")
- parser.add_argument("-n", "--loops", default=1, help="number of loop per transfer (allow more precision on speed calculation for small transfers)")
- parser.add_argument("-r", "--random", action="store_true", help="use random data")
- parser.add_argument("-c", "--continuous", action="store_true", help="continuous mode (Escape to exit)")
- parser.add_argument("-i", "--identify", action="store_true", help="only run identify")
- parser.add_argument("-t", "--software_timer", action="store_true", help="use software timer")
- parser.add_argument("-a", "--random_addressing", action="store_true", help="use random addressing")
- return parser.parse_args()
-
-if __name__ == "__main__":
- args = _get_args()
- wb = UARTWishboneBridgeDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
- wb.open()
- # # #
- identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
- generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist")
- checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
-
- identify.run()
- identify.hdd_info()
-
- if not int(args.identify):
- sector = 0
- count = int(args.transfer_size)*KB//logical_sector_size
- loops = int(args.loops)
- length = int(args.total_length)*MB
- random = int(args.random)
- continuous = int(args.continuous)
- sw_timer = int(args.software_timer)
- random_addressing = int(args.random_addressing)
-
- run_sectors = 0
- try:
- while ((run_sectors*logical_sector_size < length) or continuous) and (sector < identify.total_sectors):
- retry = 0
- # generator (write data to HDD)
- write_done = False
- while not write_done:
- write_aborted, write_errors, write_speed = generator.run(sector, count, loops, random, True, not sw_timer)
- write_done = not write_aborted
- if not write_done:
- retry += 1
-
- # checker (read and check data from HDD)
- read_done = False
- while not read_done:
- read_aborted, read_errors, read_speed = checker.run(sector, count, loops, random, True, not sw_timer)
- read_done = not read_aborted
- if not read_done:
- retry += 1
-
- ratio = identify.data_width.read()//32
- print("sector={:d}({:d}MB) wr_speed={:4.2f}MB/s rd_speed={:4.2f}MB/s errors={:d} retry={:d}".format(
- sector,
- int(run_sectors*logical_sector_size/MB)*ratio,
- write_speed/MB*ratio,
- read_speed/MB*ratio,
- write_errors + read_errors,
- retry))
- if random_addressing:
- sector = rand.randint(0, identify.total_sectors//(256*2))*256
- else:
- sector += count
- run_sectors += count
-
- except KeyboardInterrupt:
- pass
- # # #
- wb.close()
+++ /dev/null
-#!/usr/bin/env python3
-import argparse
-import importlib
-
-
-def _get_args():
- parser = argparse.ArgumentParser()
- parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
- parser.add_argument("--port", default="2", help="UART port")
- parser.add_argument("--baudrate", default=115200, help="UART baudrate")
- parser.add_argument("--ip_address", default="192.168.0.42", help="Etherbone IP address")
- parser.add_argument("--udp_port", default=20000, help="Etherbone UDP port")
- parser.add_argument("--busword", default=32, help="CSR busword")
-
- parser.add_argument("test", nargs="+", help="specify a test")
-
- return parser.parse_args()
-
-if __name__ == "__main__":
- args = _get_args()
- if args.bridge == "uart":
- from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver
- port = args.port if not args.port.isdigit() else int(args.port)
- wb = UARTWishboneBridgeDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
- elif args.bridge == "etherbone":
- from misoclib.com.liteth.software.wishbone import LiteETHWishboneDriver
- wb = LiteETHWishboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
- else:
- ValueError("Invalid bridge {}".format(args.bridge))
-
- def _import(name):
- return importlib.import_module(name)
-
- for test in args.test:
- t = _import(test)
- t.main(wb)
+++ /dev/null
-import sys
-from tools import *
-from bist import *
-from misoclib.tools.litescope.software.driver.la import LiteScopeLADriver
-
-
-def main(wb):
- la = LiteScopeLADriver(wb.regs, "la", debug=True)
- identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
- generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist")
- checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
- wb.open()
- regs = wb.regs
- # # #
- trig = "now"
- if len(sys.argv) < 2:
- print("No trigger condition, triggering immediately!")
- else:
- trig = sys.argv[1]
-
- conditions = {}
- conditions["now"] = {}
- conditions["id_cmd"] = {
- "sata_command_tx_sink_stb": 1,
- "sata_command_tx_sink_payload_identify": 1,
- }
- conditions["id_resp"] = {
- "source_source_payload_data": primitives["X_RDY"],
- }
- conditions["wr_cmd"] = {
- "sata_command_tx_sink_stb": 1,
- "sata_command_tx_sink_payload_write": 1,
- }
- conditions["wr_resp"] = {
- "sata_command_rx_source_stb": 1,
- "sata_command_rx_source_payload_write": 1,
- }
- conditions["rd_cmd"] = {
- "sata_command_tx_sink_stb": 1,
- "sata_command_tx_sink_payload_read": 1,
- }
- conditions["rd_resp"] = {
- "sata_command_rx_source_stb": 1,
- "sata_command_rx_source_payload_read": 1,
- }
-
- la.configure_term(port=0, cond=conditions[trig])
- la.configure_sum("term")
-
- # Run Logic Analyzer
- la.run(offset=64, length=1024)
-
- #identify.run(blocking=False)
- generator.run(0, 2, 1, 0, blocking=False)
- #checker.run(0, 2, 1, 0, blocking=False)
-
- while not la.done():
- pass
-
- la.upload()
- la.save("dump.vcd")
- # # #
- wb.close()
-
- f = open("dump_link.txt", "w")
- data = link_trace(la,
- tx_data_name="sink_sink_payload_data",
- rx_data_name="source_source_payload_data"
- )
- f.write(data)
- f.close()
+++ /dev/null
-import sys
-from bist import *
-from misoclib.tools.litescope.software.driver.la import LiteScopeLADriver
-
-
-def main(wb):
- identifys = []
- generators = []
- checkers = []
- for i in range(4):
- identifys.append(LiteSATABISTIdentifyDriver(wb.regs, "sata_bist{:d}".format(i)))
- generators.append(LiteSATABISTGeneratorDriver(wb.regs, "sata_bist{:d}".format(i)))
- checkers.append(LiteSATABISTCheckerDriver(wb.regs, "sata_bist{:d}".format(i)))
-
- wb.open()
- regs = wb.regs
- # # #
-
- print("Identify HDDs:")
- print("-"*80)
- for i, identify in enumerate(identifys):
- identify.run()
- print("HDD{:d}:".format(i))
- print("-"*40)
- identify.hdd_info()
- print("")
-
- print("Test Mirroring:")
- print("-"*80)
- errors = 0
- for sector in range(8):
- # Write with one generator, verify with all checkers.
- # Use generator number as sector offset to ensure we
- # are not reading data written by another generator.
- for offset, generator in enumerate(generators):
- generator.run(sector + offset, 1024, 1, 1)
- for checker in checkers:
- a, e, s = checker.run(sector + offset, 1024, 1, 1)
- errors += e
- print("errors {:d}".format(errors))
-
- # # #
- wb.close()
+++ /dev/null
-def main(wb):
- wb.open()
- regs = wb.regs
- # # #
- print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
- print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
- print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
- # # #
- wb.close()
+++ /dev/null
-from misoclib.tools.litescope.software.dump import *
-
-primitives = {
- "ALIGN": 0x7B4A4ABC,
- "CONT": 0X9999AA7C,
- "SYNC": 0xB5B5957C,
- "R_RDY": 0x4A4A957C,
- "R_OK": 0x3535B57C,
- "R_ERR": 0x5656B57C,
- "R_IP": 0X5555B57C,
- "X_RDY": 0x5757B57C,
- "CONT": 0x9999AA7C,
- "WTRM": 0x5858B57C,
- "SOF": 0x3737B57C,
- "EOF": 0xD5D5B57C,
- "HOLD": 0xD5D5AA7C,
- "HOLDA": 0X9595AA7C
-}
-
-
-def decode_primitive(dword):
- for k, v in primitives.items():
- if dword == v:
- return k
- return ""
-
-
-def link_trace(la, tx_data_name, rx_data_name):
- r = ""
- dump = Dump()
- dump.add_from_layout(la.layout, la.data)
-
- for var in dump.vars:
- if var.name == tx_data_name:
- tx_data = var.values
- if var.name == rx_data_name:
- rx_data = var.values
-
- for i in range(len(tx_data)):
- tx = "{:08x} ".format(tx_data[i])
- tx += decode_primitive(tx_data[i])
- tx += " "*(16-len(tx))
-
- rx = "{:08x} ".format(rx_data[i])
- rx += decode_primitive(rx_data[i])
- rx += " "*(16-len(rx))
-
- r += tx + rx + "\n"
-
- return r
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
-from misoclib.mem.litesata.frontend.arbiter import LiteSATAArbiter
-from misoclib.mem.litesata.frontend.striping import LiteSATAStriping
-from misoclib.mem.litesata.frontend.bist import LiteSATABIST
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.frontend.common import *
-
-from migen.genlib.roundrobin import *
-
-
-class LiteSATAArbiter(Module):
- def __init__(self, users, master):
- self.rr = RoundRobin(len(users))
- self.submodules += self.rr
- self.grant = self.rr.grant
- cases = {}
- for i, slave in enumerate(users):
- sink, source = slave.sink, slave.source
- start = Signal()
- done = Signal()
- ongoing = Signal()
- self.comb += [
- start.eq(sink.stb & sink.sop),
- done.eq(source.stb & source.last & source.eop & source.ack)
- ]
- self.sync += \
- If(start,
- ongoing.eq(1)
- ).Elif(done,
- ongoing.eq(0)
- )
- self.comb += self.rr.request[i].eq((start | ongoing) & ~done)
- cases[i] = [users[i].connect(master)]
- self.comb += Case(self.grant, cases)
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.core.link.scrambler import Scrambler
-
-from migen.bank.description import *
-
-
-class LiteSATABISTGenerator(Module):
- def __init__(self, user_port):
- self.start = Signal()
- self.sector = Signal(48)
- self.count = Signal(16)
- self.random = Signal()
-
- self.done = Signal()
- self.aborted = Signal()
- self.errors = Signal(32) # Note: Not used for writes
-
- # # #
-
- n = flen(user_port.sink.data)//32
-
- source, sink = user_port.sink, user_port.source
-
- counter = Counter(32)
- self.submodules += counter
-
- scrambler = scrambler = InsertReset(Scrambler())
- self.submodules += scrambler
- self.comb += [
- scrambler.reset.eq(counter.reset),
- scrambler.ce.eq(counter.ce)
- ]
-
- self.fsm = fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
- fsm.act("IDLE",
- self.done.eq(1),
- counter.reset.eq(1),
- If(self.start,
- NextState("SEND_CMD_AND_DATA")
- )
- )
- self.comb += [
- source.sop.eq(counter.value == 0),
- source.eop.eq(counter.value == (logical_sector_size//4*self.count)-1),
- source.write.eq(1),
- source.sector.eq(self.sector),
- source.count.eq(self.count),
- If(self.random,
- source.data.eq(Replicate(scrambler.value, n))
- ).Else(
- source.data.eq(Replicate(counter.value, n))
- )
- ]
- fsm.act("SEND_CMD_AND_DATA",
- source.stb.eq(1),
- If(source.stb & source.ack,
- counter.ce.eq(1),
- If(source.eop,
- NextState("WAIT_ACK")
- )
- )
- )
- fsm.act("WAIT_ACK",
- sink.ack.eq(1),
- If(sink.stb,
- NextState("IDLE")
- )
- )
- self.sync += If(sink.stb & sink.ack, self.aborted.eq(sink.failed))
-
-
-class LiteSATABISTChecker(Module):
- def __init__(self, user_port):
- self.start = Signal()
- self.sector = Signal(48)
- self.count = Signal(16)
- self.random = Signal()
-
- self.done = Signal()
- self.aborted = Signal()
- self.errors = Signal(32)
-
- # # #
-
- n = flen(user_port.sink.data)//32
-
- source, sink = user_port.sink, user_port.source
-
- counter = Counter(32)
- error_counter = Counter(32)
- self.submodules += counter, error_counter
- self.comb += self.errors.eq(error_counter.value)
-
- scrambler = InsertReset(Scrambler())
- self.submodules += scrambler
- self.comb += [
- scrambler.reset.eq(counter.reset),
- scrambler.ce.eq(counter.ce)
- ]
-
- self.fsm = fsm = FSM(reset_state="IDLE")
- self.submodules += self.fsm
- fsm.act("IDLE",
- self.done.eq(1),
- counter.reset.eq(1),
- If(self.start,
- error_counter.reset.eq(1),
- NextState("SEND_CMD")
- )
- )
- self.comb += [
- source.sop.eq(1),
- source.eop.eq(1),
- source.read.eq(1),
- source.sector.eq(self.sector),
- source.count.eq(self.count),
- ]
- fsm.act("SEND_CMD",
- source.stb.eq(1),
- If(source.ack,
- counter.reset.eq(1),
- NextState("WAIT_ACK")
- )
- )
- fsm.act("WAIT_ACK",
- If(sink.stb & sink.read,
- NextState("RECEIVE_DATA")
- )
- )
- expected_data = Signal(n*32)
- self.comb += \
- If(self.random,
- expected_data.eq(Replicate(scrambler.value, n))
- ).Else(
- expected_data.eq(Replicate(counter.value, n))
- )
- fsm.act("RECEIVE_DATA",
- sink.ack.eq(1),
- If(sink.stb,
- counter.ce.eq(1),
- If(sink.data != expected_data,
- error_counter.ce.eq(~sink.last)
- ),
- If(sink.eop,
- If(sink.last,
- NextState("IDLE")
- ).Else(
- NextState("WAIT_ACK")
- )
- )
- )
- )
- self.sync += If(sink.stb & sink.ack, self.aborted.eq(sink.failed))
-
-
-class LiteSATABISTUnitCSR(Module, AutoCSR):
- def __init__(self, bist_unit):
- self._start = CSR()
- self._sector = CSRStorage(48)
- self._count = CSRStorage(16)
- self._loops = CSRStorage(8)
- self._random = CSRStorage()
-
- self._done = CSRStatus()
- self._aborted = CSRStatus()
- self._errors = CSRStatus(32)
- self._cycles = CSRStatus(32)
-
- # # #
-
- self.submodules += bist_unit
-
- start = self._start.r & self._start.re
- done = self._done.status
- loops = self._loops.storage
-
- self.comb += [
- bist_unit.sector.eq(self._sector.storage),
- bist_unit.count.eq(self._count.storage),
- bist_unit.random.eq(self._random.storage),
-
- self._aborted.status.eq(bist_unit.aborted),
- self._errors.status.eq(bist_unit.errors)
- ]
-
- self.fsm = fsm = FSM(reset_state="IDLE")
- loop_counter = Counter(8)
- self.submodules += fsm, loop_counter
- fsm.act("IDLE",
- self._done.status.eq(1),
- loop_counter.reset.eq(1),
- If(start,
- NextState("CHECK")
- )
- )
- fsm.act("CHECK",
- If(loop_counter.value < loops,
- NextState("START")
- ).Else(
- NextState("IDLE")
- )
- )
- fsm.act("START",
- bist_unit.start.eq(1),
- NextState("WAIT_DONE")
- )
- fsm.act("WAIT_DONE",
- If(bist_unit.done,
- loop_counter.ce.eq(1),
- NextState("CHECK")
- )
- )
-
- cycles_counter = Counter(32)
- self.submodules += cycles_counter
- self.sync += [
- cycles_counter.reset.eq(start),
- cycles_counter.ce.eq(~fsm.ongoing("IDLE")),
- self._cycles.status.eq(cycles_counter.value)
- ]
-
-
-class LiteSATABISTIdentify(Module):
- def __init__(self, user_port):
- self.start = Signal()
- self.done = Signal()
- self.data_width = flen(user_port.sink.data)
-
- fifo = SyncFIFO([("data", 32)], 512, buffered=True)
- self.submodules += fifo
- self.source = fifo.source
-
- # # #
-
- source, sink = user_port.sink, user_port.source
-
- self.fsm = fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
- fsm.act("IDLE",
- self.done.eq(1),
- If(self.start,
- NextState("SEND_CMD")
- )
- )
- self.comb += [
- source.sop.eq(1),
- source.eop.eq(1),
- source.identify.eq(1),
- ]
- fsm.act("SEND_CMD",
- source.stb.eq(1),
- If(source.stb & source.ack,
- NextState("WAIT_ACK")
- )
- )
- fsm.act("WAIT_ACK",
- If(sink.stb & sink.identify,
- NextState("RECEIVE_DATA")
- )
- )
- self.comb += fifo.sink.data.eq(sink.data)
- fsm.act("RECEIVE_DATA",
- sink.ack.eq(fifo.sink.ack),
- If(sink.stb,
- fifo.sink.stb.eq(1),
- If(sink.eop,
- NextState("IDLE")
- )
- )
- )
-
-
-class LiteSATABISTIdentifyCSR(Module, AutoCSR):
- def __init__(self, bist_identify):
- self._start = CSR()
- self._done = CSRStatus()
- self._data_width = CSRStatus(16, reset=bist_identify.data_width)
- self._source_stb = CSRStatus()
- self._source_ack = CSR()
- self._source_data = CSRStatus(32)
-
- # # #
-
- self.submodules += bist_identify
- self.comb += [
- bist_identify.start.eq(self._start.r & self._start.re),
- self._done.status.eq(bist_identify.done),
-
- self._source_stb.status.eq(bist_identify.source.stb),
- self._source_data.status.eq(bist_identify.source.data),
- bist_identify.source.ack.eq(self._source_ack.r & self._source_ack.re)
- ]
-
-
-class LiteSATABIST(Module, AutoCSR):
- def __init__(self, crossbar, with_csr=False):
- generator = LiteSATABISTGenerator(crossbar.get_port())
- checker = LiteSATABISTChecker(crossbar.get_port())
- identify = LiteSATABISTIdentify(crossbar.get_port())
- if with_csr:
- generator = LiteSATABISTUnitCSR(generator)
- checker = LiteSATABISTUnitCSR(checker)
- identify = LiteSATABISTIdentifyCSR(identify)
- self.submodules.generator = generator
- self.submodules.checker = checker
- self.submodules.identify = identify
+++ /dev/null
-from misoclib.mem.litesata.common import *
-
-
-class LiteSATAMasterPort:
- def __init__(self, dw):
- self.source = Source(command_tx_description(dw))
- self.sink = Sink(command_rx_description(dw))
-
- def connect(self, slave):
- return [
- Record.connect(self.source, slave.sink),
- Record.connect(slave.source, self.sink)
- ]
-
-
-class LiteSATASlavePort:
- def __init__(self, dw):
- self.sink = Sink(command_tx_description(dw))
- self.source = Source(command_rx_description(dw))
-
- def connect(self, master):
- return [
- Record.connect(self.sink, master.source),
- Record.connect(master.sink, self.source)
- ]
-
-
-class LiteSATAUserPort(LiteSATASlavePort):
- def __init__(self, dw):
- LiteSATASlavePort.__init__(self, dw)
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.frontend.common import *
-from misoclib.mem.litesata.frontend.arbiter import LiteSATAArbiter
-
-
-class LiteSATACrossbar(Module):
- def __init__(self, controller):
- self.dw = flen(controller.sink.data)
- self.users = []
- self.master = LiteSATAMasterPort(self.dw)
- self.comb += [
- self.master.source.connect(controller.sink),
- controller.source.connect(self.master.sink)
- ]
-
- def get_port(self):
- port = LiteSATAUserPort(self.dw)
- self.users += [port]
- return port
-
- def get_ports(self, n):
- ports = []
- for i in range(n):
- ports.append(self.get_port())
- return ports
-
- def do_finalize(self):
- arbiter = LiteSATAArbiter(self.users, self.master)
- self.submodules += arbiter
+++ /dev/null
-from migen.actorlib.packet import Arbiter, Dispatcher, Status
-from migen.flow.plumbing import Multiplexer
-
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.frontend.common import *
-from misoclib.mem.litesata.frontend.striping import LiteSATAStripingTX, LiteSATAStripingRX
-
-
-class LiteSATAMirroringCtrl(Module):
- def __init__(self, n):
- self.new_cmds = Signal(n)
- self.ack_cmds = Signal(n)
-
- self.reading = Signal()
- self.writing = Signal()
-
- self.wants_write = Signal()
- self.write_sel = Signal(max=n)
-
- # # #
-
- pending_cmds = Signal(n)
- self.sync += pending_cmds.eq(self.new_cmds | (pending_cmds & ~self.ack_cmds))
- can_commute = Signal()
- self.comb += can_commute.eq((pending_cmds | self.new_cmds) == 0)
-
- self.fsm = fsm = FSM(reset_state="READ")
- self.submodules += fsm
- fsm.act("READ",
- self.reading.eq(1),
- If(self.wants_write & can_commute,
- NextState("WRITE")
- )
- )
- fsm.act("WRITE",
- self.writing.eq(1),
- If(~self.wants_write & can_commute,
- NextState("READ")
- )
- )
-
-
-class LiteSATAMirroringTX(Module):
- def __init__(self, n, dw, ctrl):
- self.sinks = sinks = [Sink(command_tx_description(dw)) for i in range(n)]
- self.sources = sources = [Source(command_tx_description(dw)) for i in range(n)]
-
- # # #
-
- wants_write = Signal()
-
- reading = Signal()
- writing = Signal()
-
- reads = [Sink(command_tx_description(dw)) for i in range(dw)]
- writes = [Sink(command_tx_description(dw)) for i in range(dw)]
- for sink, read, write in zip(sinks, reads, writes):
- read_stall = Signal()
- read_status = Status(read)
- self.submodules += read_status
- self.comb += [
- Record.connect(sink, read, leave_out=set(["stb", "ack"])),
- Record.connect(sink, write, leave_out=set(["stb", "ack"])),
- read.stb.eq(sink.stb & (sink.read | sink.identify) & ~read_stall),
- write.stb.eq(sink.stb & sink.write),
- If(sink.read | sink.identify,
- sink.ack.eq((read.ack & ~read_stall))
- ).Else(
- sink.ack.eq(write.ack)
- )
- ]
- self.sync += \
- If(~ctrl.wants_write,
- read_stall.eq(0)
- ).Elif(~read_status.ongoing,
- read_stall.eq(1)
- )
-
- write_striper = LiteSATAStripingTX(n, dw, mirroring_mode=True)
- write_arbiter = Arbiter(writes, write_striper.sink)
- self.submodules += write_striper, write_arbiter
-
- for i in range(n):
- source_status = Status(sources[i])
- self.submodules += source_status
- self.comb += [
- If(ctrl.reading,
- Record.connect(reads[i], sources[i]) # independent reads
- ).Elif(ctrl.writing,
- Record.connect(write_striper.sources[i], sources[i]) # identical writes
- ),
- ctrl.new_cmds[i].eq(source_status.eop)
- ]
- write_striper_sink_status = Status(write_striper.sink)
- self.submodules += write_striper_sink_status
- self.comb += [
- ctrl.wants_write.eq(write_striper_sink_status.ongoing),
- ctrl.write_sel.eq(write_arbiter.rr.grant)
- ]
-
-
-class LiteSATAMirroringRX(Module):
- def __init__(self, n, dw, ctrl):
- self.sinks = sinks = [Sink(command_rx_description(dw)) for i in range(n)]
- self.sources = sources = [Source(command_rx_description(dw)) for i in range(n)]
-
- # # #
-
- muxs = [Multiplexer(command_rx_description(dw), 2) for i in range(n)]
- self.submodules += muxs
-
- writes = [mux.sink0 for mux in muxs]
- reads = [mux.sink1 for mux in muxs]
-
- for mux, source in zip(muxs, sources):
- self.comb += [
- mux.sel.eq(ctrl.reading),
- Record.connect(mux.source, source)
- ]
-
- write_striper = LiteSATAStripingRX(n, dw, mirroring_mode=True)
- write_dispatcher = Dispatcher(write_striper.source, writes)
- self.comb += write_dispatcher.sel.eq(ctrl.write_sel)
- self.submodules += write_striper, write_dispatcher
-
- for i in range(n):
- sink_status = Status(sinks[i])
- self.submodules += sink_status
- self.comb += [
- Record.connect(sinks[i], reads[i], leave_out=set(["stb", "ack"])),
- Record.connect(sinks[i], write_striper.sinks[i], leave_out=set(["stb", "ack"])),
- reads[i].stb.eq(sinks[i].stb & ctrl.reading),
- write_striper.sinks[i].stb.eq(sinks[i].stb & ctrl.writing),
- sinks[i].ack.eq(reads[i].ack | write_striper.sinks[i].ack),
- ctrl.ack_cmds[i].eq(sink_status.eop & sinks[i].last)
- ]
-
-
-class LiteSATAMirroring(Module):
- """SATA Mirroring
-
- The mirroring module handles N controllers and provides N ports.
- Each port has its dedicated controller for reads:
- port0 <----> controller0
- portX <----> controllerX
- portN <----> controllerN
-
- Writes are mirrored on each controller:
- (port0 write) | (portN write)
- port0 ----------+----> controller0 | port0 (stalled) +-----> controller0
- portX (stalled) +----> controllerX | portX (stalled) +-----> controllerX
- portN (stalled) +----> controllerN | portN ----------+-----> controllerN
-
- Writes have priority on reads. When a write is presented on one of the port, the
- module waits for all ongoing reads to finish and commute to write mode. Once all writes are
- serviced it returns to read mode.
-
- Characteristics:
- - port's visible capacity = controller's visible capacity
- - total writes throughput = (slowest) controller's throughput
- - total reads throughput = N x controller's throughput
-
- Can be used for data redundancy and/or to increase total reads speed.
- """
- def __init__(self, controllers):
- n = len(controllers)
- dw = flen(controllers[0].sink.data)
- self.ports = [LiteSATAUserPort(dw) for i in range(n)]
-
- # # #
-
- self.submodules.ctrl = LiteSATAMirroringCtrl(n)
- self.submodules.tx = LiteSATAMirroringTX(n, dw, self.ctrl)
- self.submodules.rx = LiteSATAMirroringRX(n, dw, self.ctrl)
- for i in range(n):
- self.comb += [
- Record.connect(self.ports[i].sink, self.tx.sinks[i]),
- Record.connect(self.tx.sources[i], controllers[i].sink),
-
- Record.connect(controllers[i].source, self.rx.sinks[i]),
- Record.connect(self.rx.sources[i], self.ports[i].source)
- ]
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.frontend.common import *
-
-
-class LiteSATAStripingTX(Module):
- """SATA Striping TX
-
- Split cmds and writes data on N different controllers.
-
- This module provides a mirroring_mode that is used by the mirroring module to
- dispatch identicals writes to the controllers. This avoid code duplication in
- between striping and mirroring modules. In this special case, port's data width
- is dw (same as controllers)
- """
- def __init__(self, n, dw, mirroring_mode=False):
- self.sink = sink = Sink(command_tx_description(dw*n if not mirroring_mode else dw))
- self.sources = sources = [Source(command_tx_description(dw)) for i in range(n)]
-
- # # #
-
- split = Signal()
-
- already_acked = Signal(n)
- self.sync += If(split & sink.stb,
- already_acked.eq(already_acked | Cat(*[s.ack for s in sources])),
- If(sink.ack, already_acked.eq(0))
- )
-
- self.fsm = fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
- fsm.act("IDLE",
- sink.ack.eq(0),
- If(sink.stb & sink.sop,
- NextState("SPLIT")
- ).Else(
- sink.ack.eq(1)
- )
- )
-
- # split data and ctrl signals (except stb & ack managed in fsm)
- for i, s in enumerate(sources):
- self.comb += Record.connect(sink, s, leave_out=set(["stb", "ack", "data"]))
- if mirroring_mode:
- self.comb += s.data.eq(sink.data)
- else:
- self.comb += s.data.eq(sink.data[i*dw:(i+1)*dw])
-
- fsm.act("SPLIT",
- split.eq(1),
- [s.stb.eq(sink.stb & ~already_acked[i]) for i, s in enumerate(sources)],
- sink.ack.eq(optree("&", [s.ack | already_acked[i] for i, s in enumerate(sources)])),
- If(sink.stb & sink.eop & sink.ack,
- NextState("IDLE")
- )
- )
-
-class LiteSATAStripingRX(Module):
- """SATA Striping RX
-
- Combine acknowledges and reads data from N different controllers.
-
- This module provides a mirroring_mode that is used by the mirroring module to
- dispatch identicals writes to the controllers. This avoid code duplication in
- between striping and mirroring modules. In this special case, port's data width
- is dw (same as controllers)
- """
- def __init__(self, n, dw, mirroring_mode=False):
- self.sinks = sinks = [Sink(command_rx_description(dw)) for i in range(n)]
- self.source = source = Source(command_rx_description(dw*n if not mirroring_mode else dw))
-
- # # #
-
- sop = Signal()
- self.comb += sop.eq(optree("&", [s.stb & s.sop for s in sinks]))
-
- self.fsm = fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
- fsm.act("IDLE",
- If(sop,
- NextState("COMBINE")
- )
- )
-
- # use first sink for ctrl signals (except for stb, ack & failed)
- self.comb += Record.connect(sinks[0], source, leave_out=set(["stb", "ack", "failed", "data"]))
- # combine datas
- if mirroring_mode:
- self.comb += source.data.eq(0) # mirroring only used for writes
- else:
- for i, s in enumerate(sinks):
- self.comb += source.data[i*dw:(i+1)*dw].eq(s.data)
-
-
- fsm.act("COMBINE",
- source.failed.eq(optree("|", [s.failed for s in sinks])), # XXX verify this is enough
- source.stb.eq(optree("&", [s.stb for s in sinks])),
- [s.ack.eq(source.stb & source.ack) for s in sinks],
- If(source.stb & source.eop & source.ack,
- NextState("IDLE")
- )
- )
-
-
-class LiteSATAStriping(Module):
- """SATA Striping
-
- Segment data so that data is stored on N different controllers.
- +----> controller0 (dw)
- port (N*dw) <----+----> controllerX (dw)
- +----> controllerN (dw)
-
- Characteristics:
- - port's visible capacity = N x controller's visible capacity
- - port's throughput = N x (slowest) controller's throughput
-
- Can be used to increase capacity and writes/reads throughput.
- """
- def __init__(self, controllers):
-
- # # #
- n = len(controllers)
- dw = flen(controllers[0].sink.data)
-
- self.submodules.tx = LiteSATAStripingTX(n, dw)
- self.submodules.rx = LiteSATAStripingRX(n, dw)
- for i in range(n):
- self.comb += [
- Record.connect(self.tx.sources[i], controllers[i].sink),
- Record.connect(controllers[i].source, self.rx.sinks[i])
- ]
- self.sink, self.source = self.tx.sink, self.rx.source
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.phy.ctrl import *
-from misoclib.mem.litesata.phy.datapath import *
-
-
-class LiteSATAPHY(Module):
- def __init__(self, device, clock_pads_or_refclk, pads, revision, clk_freq):
- self.clock_pads = clock_pads_or_refclk
- self.pads = pads
- self.revision = revision
-
- # Transceiver / Clocks
- if device[:3] == "xc7": # Kintex 7
- from misoclib.mem.litesata.phy.k7.trx import K7LiteSATAPHYTRX
- from misoclib.mem.litesata.phy.k7.crg import K7LiteSATAPHYCRG
- self.submodules.trx = K7LiteSATAPHYTRX(pads, revision)
- self.submodules.crg = K7LiteSATAPHYCRG(clock_pads_or_refclk, pads, self.trx, revision, clk_freq)
- else:
- raise NotImplementedError
-
- # Control
- self.submodules.ctrl = LiteSATAPHYCtrl(self.trx, self.crg, clk_freq)
-
- # Datapath
- self.submodules.datapath = LiteSATAPHYDatapath(self.trx, self.ctrl)
- self.sink, self.source = self.datapath.sink, self.datapath.source
+++ /dev/null
-from misoclib.mem.litesata.common import *
-
-
-class LiteSATAPHYCtrl(Module):
- def __init__(self, trx, crg, clk_freq):
- self.clk_freq = clk_freq
- self.ready = Signal()
- self.sink = sink = Sink(phy_description(32))
- self.source = source = Source(phy_description(32))
-
- # # #
-
- self.comb += [
- source.stb.eq(1),
- sink.ack.eq(1)
- ]
-
- retry_timer = WaitTimer(self.us(10000))
- align_timer = WaitTimer(self.us(873))
- self.submodules += align_timer, retry_timer
-
- align_det = Signal()
- misalign_det = Signal()
- non_align_counter = Counter(4)
- self.submodules += non_align_counter
-
- self.comb += [
- If(sink.stb,
- align_det.eq((self.sink.charisk == 0b0001) &
- (self.sink.data == primitives["ALIGN"])),
- misalign_det.eq((self.sink.charisk & 0b1010) != 0)
- )
- ]
-
- self.fsm = fsm = InsertReset(FSM(reset_state="RESET"))
- self.submodules += fsm
- self.comb += fsm.reset.eq(retry_timer.done | align_timer.done)
- fsm.act("RESET",
- trx.tx_idle.eq(1),
- non_align_counter.reset.eq(1),
- If(crg.ready,
- NextState("COMINIT")
- )
- )
- fsm.act("COMINIT",
- trx.tx_idle.eq(1),
- trx.tx_cominit_stb.eq(1),
- If(trx.tx_cominit_ack & ~trx.rx_cominit_stb,
- NextState("AWAIT_COMINIT")
- )
- )
- fsm.act("AWAIT_COMINIT",
- trx.tx_idle.eq(1),
- retry_timer.wait.eq(1),
- If(trx.rx_cominit_stb,
- NextState("AWAIT_NO_COMINIT")
- )
- )
- fsm.act("AWAIT_NO_COMINIT",
- trx.tx_idle.eq(1),
- retry_timer.wait.eq(1),
- If(~trx.rx_cominit_stb,
- NextState("CALIBRATE")
- )
- )
- fsm.act("CALIBRATE",
- trx.tx_idle.eq(1),
- NextState("COMWAKE"),
- )
- fsm.act("COMWAKE",
- trx.tx_idle.eq(1),
- trx.tx_comwake_stb.eq(1),
- If(trx.tx_comwake_ack,
- NextState("AWAIT_COMWAKE")
- )
- )
- fsm.act("AWAIT_COMWAKE",
- trx.tx_idle.eq(1),
- retry_timer.wait.eq(1),
- If(trx.rx_comwake_stb,
- NextState("AWAIT_NO_COMWAKE")
- )
- )
- fsm.act("AWAIT_NO_COMWAKE",
- trx.tx_idle.eq(1),
- If(~trx.rx_comwake_stb,
- NextState("AWAIT_NO_RX_IDLE")
- )
- )
- fsm.act("AWAIT_NO_RX_IDLE",
- trx.tx_idle.eq(0),
- source.data.eq(0x4A4A4A4A), # D10.2
- source.charisk.eq(0b0000),
- align_timer.wait.eq(1),
- If(~trx.rx_idle,
- NextState("AWAIT_ALIGN"),
- crg.tx_reset.eq(1),
- crg.rx_reset.eq(1)
- )
- )
- fsm.act("AWAIT_ALIGN",
- trx.tx_idle.eq(0),
- source.data.eq(0x4A4A4A4A), # D10.2
- source.charisk.eq(0b0000),
- trx.rx_align.eq(1),
- align_timer.wait.eq(1),
- If(align_det & ~trx.rx_idle,
- NextState("SEND_ALIGN")
- )
- )
- fsm.act("SEND_ALIGN",
- trx.tx_idle.eq(0),
- trx.rx_align.eq(1),
- align_timer.wait.eq(1),
- source.data.eq(primitives["ALIGN"]),
- source.charisk.eq(0b0001),
- If(sink.stb,
- If(sink.data[0:8] == 0x7C,
- non_align_counter.ce.eq(1)
- ).Else(
- non_align_counter.reset.eq(1)
- )
- ),
- If(non_align_counter.value == 3,
- NextState("READY")
- )
- )
-
- # wait alignement stability for 100ms before declaring ctrl is ready,
- # reset the RX part of the transceiver when misalignment is detected.
- stability_timer = WaitTimer(100*clk_freq//1000)
- self.submodules += stability_timer
-
- fsm.act("READY",
- trx.tx_idle.eq(0),
- trx.rx_align.eq(1),
- source.data.eq(primitives["SYNC"]),
- source.charisk.eq(0b0001),
- stability_timer.wait.eq(1),
- self.ready.eq(stability_timer.done),
- If(trx.rx_idle,
- NextState("RESET"),
- ).Elif(misalign_det,
- crg.rx_reset.eq(1),
- NextState("REALIGN")
- )
- )
- fsm.act("REALIGN",
- If(crg.ready,
- NextState("READY")
- )
- )
-
-
-
- def us(self, t):
- clk_period_us = 1000000/self.clk_freq
- return math.ceil(t/clk_period_us)
+++ /dev/null
-from misoclib.mem.litesata.common import *
-
-
-class LiteSATAPHYDatapathRX(Module):
- def __init__(self):
- self.sink = sink = Sink(phy_description(16))
- self.source = source = Source(phy_description(32))
-
- # # #
-
- # width convertion (16 to 32) and byte alignment
- byte_alignment = Signal()
- last_charisk = Signal(2)
- last_data = Signal(16)
- self.sync.sata_rx += \
- If(sink.stb & sink.ack,
- If(sink.charisk != 0,
- byte_alignment.eq(sink.charisk[1])
- ),
- last_charisk.eq(sink.charisk),
- last_data.eq(sink.data)
- )
- converter = Converter(phy_description(16),
- phy_description(32),
- reverse=False)
- converter = InsertReset(RenameClockDomains(converter, "sata_rx"))
- self.submodules += converter
- self.comb += [
- converter.sink.stb.eq(sink.stb),
- If(byte_alignment,
- converter.sink.charisk.eq(Cat(last_charisk[1], sink.charisk[0])),
- converter.sink.data.eq(Cat(last_data[8:], sink.data[:8]))
- ).Else(
- converter.sink.charisk.eq(sink.charisk),
- converter.sink.data.eq(sink.data)
- ),
- sink.ack.eq(converter.sink.ack),
- converter.reset.eq(converter.source.charisk[2:] != 0)
- ]
-
- # clock domain crossing
- # (sata_gen3) 300MHz sata_rx clk to sys_clk
- # (sata_gen2) 150MHz sata_rx clk to sys_clk
- # (sata_gen1) 75MHz sata_rx clk to sys_clk
- # requirements:
- # due to the convertion ratio of 2, sys_clk need to be > sata_rx/2
- # source destination is always able to accept data (ack always 1)
- fifo = AsyncFIFO(phy_description(32), 4)
- fifo = RenameClockDomains(fifo, {"write": "sata_rx", "read": "sys"})
- self.submodules += fifo
- self.comb += [
- Record.connect(converter.source, fifo.sink),
- Record.connect(fifo.source, source)
- ]
-
-
-class LiteSATAPHYDatapathTX(Module):
- def __init__(self):
- self.sink = sink = Sink(phy_description(32))
- self.source = source = Source(phy_description(16))
-
- # # #
-
- # clock domain crossing
- # (sata_gen3) sys_clk to 300MHz sata_tx clk
- # (sata_gen2) sys_clk to 150MHz sata_tx clk
- # (sata_gen1) sys_clk to 75MHz sata_tx clk
- # requirements:
- # source destination is always able to accept data (ack always 1)
- fifo = AsyncFIFO(phy_description(32), 4)
- fifo = RenameClockDomains(fifo, {"write": "sys", "read": "sata_tx"})
- self.submodules += fifo
- self.comb += Record.connect(sink, fifo.sink)
-
- # width convertion (32 to 16)
- converter = Converter(phy_description(32),
- phy_description(16),
- reverse=False)
- converter = RenameClockDomains(converter, "sata_tx")
- self.submodules += converter
- self.comb += [
- Record.connect(fifo.source, converter.sink),
- Record.connect(converter.source, source)
- ]
-
-
-class LiteSATAPHYAlignInserter(Module):
- def __init__(self, ctrl):
- self.sink = sink = Sink(phy_description(32))
- self.source = source = Source(phy_description(32))
-
- # # #
-
- # send 2 ALIGN every 256 DWORDs
- # used for clock compensation between
- # HOST and device
- cnt = Signal(8)
- send = Signal()
- self.sync += \
- If(~ctrl.ready,
- cnt.eq(0)
- ).Elif(source.stb & source.ack,
- cnt.eq(cnt+1)
- )
- self.comb += [
- send.eq(cnt < 2),
- If(send,
- source.stb.eq(1),
- source.charisk.eq(0b0001),
- source.data.eq(primitives["ALIGN"]),
- sink.ack.eq(0)
- ).Else(
- source.stb.eq(sink.stb),
- source.data.eq(sink.data),
- source.charisk.eq(sink.charisk),
- sink.ack.eq(source.ack)
- )
- ]
-
-
-class LiteSATAPHYAlignRemover(Module):
- def __init__(self):
- self.sink = sink = Sink(phy_description(32))
- self.source = source = Source(phy_description(32))
-
- # # #
-
- charisk_match = sink.charisk == 0b0001
- data_match = sink.data == primitives["ALIGN"]
-
- self.comb += \
- If(sink.stb & charisk_match & data_match,
- sink.ack.eq(1),
- ).Else(
- Record.connect(sink, source)
- )
-
-
-class LiteSATAPHYDatapath(Module):
- def __init__(self, trx, ctrl):
- self.sink = sink = Sink(phy_description(32))
- self.source = source = Source(phy_description(32))
-
- # # #
-
- # TX path
- align_inserter = LiteSATAPHYAlignInserter(ctrl)
- mux = Multiplexer(phy_description(32), 2)
- tx = LiteSATAPHYDatapathTX()
- self.submodules += align_inserter, mux, tx
- self.comb += [
- mux.sel.eq(ctrl.ready),
- Record.connect(sink, align_inserter.sink),
- Record.connect(ctrl.source, mux.sink0),
- Record.connect(align_inserter.source, mux.sink1),
- Record.connect(mux.source, tx.sink),
- Record.connect(tx.source, trx.sink)
- ]
-
- # RX path
- rx = LiteSATAPHYDatapathRX()
- demux = Demultiplexer(phy_description(32), 2)
- align_remover = LiteSATAPHYAlignRemover()
- self.submodules += rx, demux, align_remover
- self.comb += [
- demux.sel.eq(ctrl.ready),
- Record.connect(trx.source, rx.sink),
- Record.connect(rx.source, demux.sink),
- Record.connect(demux.source0, ctrl.sink),
- Record.connect(demux.source1, align_remover.sink),
- Record.connect(align_remover.source, source)
- ]
+++ /dev/null
-from misoclib.mem.litesata.common import *
-
-
-class K7LiteSATAPHYCRG(Module):
- def __init__(self, clock_pads_or_refclk, pads, gtx, revision, clk_freq):
- self.tx_reset = Signal()
- self.rx_reset = Signal()
- self.ready = Signal()
-
- self.clock_domains.cd_sata_tx = ClockDomain()
- self.clock_domains.cd_sata_rx = ClockDomain()
-
- # CPLL
- # (sata_gen3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps
- # (sata_gen2 & sata_gen1) VCO still @ 3 GHz, Line rate is
- # decreased with output dividers.
- if isinstance(clock_pads_or_refclk, Signal):
- self.refclk = clock_pads_or_refclk
- else:
- self.refclk = Signal()
- clock_pads = clock_pads_or_refclk
- self.specials += Instance("IBUFDS_GTE2",
- i_CEB=0,
- i_I=clock_pads.refclk_p,
- i_IB=clock_pads.refclk_n,
- o_O=self.refclk
- )
-
- self.comb += gtx.gtrefclk0.eq(self.refclk)
-
- # TX clocking
- # (sata_gen3) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 300MHz (16-bits)
- # (sata_gen2) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 150MHz (16-bits)
- # (sata_gen1) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 75MHz (16-bits)
- mmcm_reset = Signal()
- mmcm_locked = Signal()
- mmcm_fb = Signal()
- mmcm_clk_i = Signal()
- mmcm_clk0_o = Signal()
- mmcm_div_config = {
- "sata_gen1": 16.0,
- "sata_gen2": 8.0,
- "sata_gen3": 4.0
- }
- mmcm_div = mmcm_div_config[revision]
- self.specials += [
- Instance("BUFG", i_I=gtx.txoutclk, o_O=mmcm_clk_i),
- Instance("MMCME2_ADV",
- p_BANDWIDTH="HIGH", p_COMPENSATION="ZHOLD", i_RST=mmcm_reset, o_LOCKED=mmcm_locked,
-
- # DRP
- i_DCLK=0, i_DEN=0, i_DWE=0, #o_DRDY=,
- i_DADDR=0, i_DI=0, #o_DO=,
-
- # VCO
- p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=6.666,
- p_CLKFBOUT_MULT_F=8.000, p_CLKFBOUT_PHASE=0.000, p_DIVCLK_DIVIDE=1,
- i_CLKIN1=mmcm_clk_i, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
-
- # CLK0
- p_CLKOUT0_DIVIDE_F=mmcm_div, p_CLKOUT0_PHASE=0.000, o_CLKOUT0=mmcm_clk0_o,
- ),
- Instance("BUFG", i_I=mmcm_clk0_o, o_O=self.cd_sata_tx.clk),
- ]
- self.comb += [
- gtx.txusrclk.eq(self.cd_sata_tx.clk),
- gtx.txusrclk2.eq(self.cd_sata_tx.clk)
- ]
-
- # RX clocking
- # (sata_gen3) sata_rx recovered clk @ 300MHz from GTX RXOUTCLK
- # (sata_gen2) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
- # (sata_gen1) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
- self.specials += [
- Instance("BUFG", i_I=gtx.rxoutclk, o_O=self.cd_sata_rx.clk),
- ]
- self.comb += [
- gtx.rxusrclk.eq(self.cd_sata_rx.clk),
- gtx.rxusrclk2.eq(self.cd_sata_rx.clk)
- ]
-
- # Configuration Reset
- # After configuration, GTX's resets have to stay low for at least 500ns
- # See AR43482
- startup_cycles = math.ceil(500*clk_freq/1000000000)
- startup_timer = WaitTimer(startup_cycles)
- self.submodules += startup_timer
- self.comb += startup_timer.wait.eq(~(self.tx_reset | self.rx_reset))
-
- # TX Startup FSM
- self.tx_ready = Signal()
- tx_startup_fsm = InsertReset(FSM(reset_state="IDLE"))
- self.submodules += tx_startup_fsm
- # Wait 500ns of AR43482
- tx_startup_fsm.act("IDLE",
- If(startup_timer.done,
- NextState("RESET_ALL"),
- )
- )
- # Reset CPLL, MMCM, GTX
- tx_startup_fsm.act("RESET_ALL",
- gtx.cpllreset.eq(1),
- mmcm_reset.eq(1),
- gtx.gttxreset.eq(1),
- NextState("RELEASE_CPLL"),
- )
- # Release CPLL reset and wait for lock
- tx_startup_fsm.act("RELEASE_CPLL",
- mmcm_reset.eq(1),
- gtx.gttxreset.eq(1),
- If(gtx.cplllock,
- NextState("RELEASE_MMCM"),
- )
- )
- # Release MMCM reset and wait for lock
- tx_startup_fsm.act("RELEASE_MMCM",
- gtx.gttxreset.eq(1),
- If(mmcm_locked,
- NextState("RELEASE_GTX")
- )
- )
- # Release GTX reset and wait for GTX resetdone
- # (from UG476, GTX is reseted on falling edge
- # of gttxreset)
- tx_startup_fsm.act("RELEASE_GTX",
- gtx.txuserrdy.eq(1),
- If(gtx.txresetdone,
- NextState("READY")
- )
- )
- # Start Delay alignment (Pulse)
- tx_startup_fsm.act("ALIGN",
- gtx.txuserrdy.eq(1),
- gtx.txdlyreset.eq(1),
- NextState("WAIT_ALIGN")
- )
- # Wait Delay alignment
- tx_startup_fsm.act("WAIT_ALIGN",
- gtx.txuserrdy.eq(1),
- If(gtx.txdlyresetdone,
- NextState("READY")
- )
- )
- tx_startup_fsm.act("READY",
- gtx.txuserrdy.eq(1),
- self.tx_ready.eq(1)
- )
-
- tx_ready_timer = WaitTimer(1*clk_freq//1000)
- self.submodules += tx_ready_timer
- self.comb += [
- tx_ready_timer.wait.eq(~self.tx_ready),
- tx_startup_fsm.reset.eq(self.tx_reset | tx_ready_timer.done),
- ]
-
-
- # RX Startup FSM
- self.rx_ready = Signal()
- rx_startup_fsm = InsertReset(FSM(reset_state="IDLE"))
- self.submodules += rx_startup_fsm
-
- cdr_stable_timer = WaitTimer(2048)
- self.submodules += cdr_stable_timer
-
- # Wait 500ns of AR43482
- rx_startup_fsm.act("IDLE",
- If(startup_timer.done,
- NextState("RESET_GTX"),
- )
- )
- # Reset GTX
- rx_startup_fsm.act("RESET_GTX",
- gtx.gtrxreset.eq(1),
- NextState("WAIT_CPLL")
- )
- # Wait for CPLL lock
- rx_startup_fsm.act("WAIT_CPLL",
- gtx.gtrxreset.eq(1),
- If(gtx.cplllock,
- NextState("RELEASE_GTX")
- )
- )
- # Release GTX reset and wait for GTX resetdone
- # (from UG476, GTX is reseted on falling edge
- # of gttxreset)
- rx_startup_fsm.act("RELEASE_GTX",
- gtx.rxuserrdy.eq(1),
- cdr_stable_timer.wait.eq(1),
- If(gtx.rxresetdone & cdr_stable_timer.done,
- NextState("ALIGN")
- )
- )
- # Start Delay alignment (Pulse)
- rx_startup_fsm.act("ALIGN",
- gtx.rxuserrdy.eq(1),
- gtx.rxdlyreset.eq(1),
- NextState("WAIT_ALIGN")
- )
- # Wait Delay alignment
- rx_startup_fsm.act("WAIT_ALIGN",
- gtx.rxuserrdy.eq(1),
- If(gtx.rxdlyresetdone,
- NextState("READY")
- )
- )
- rx_startup_fsm.act("READY",
- gtx.rxuserrdy.eq(1),
- self.rx_ready.eq(1)
- )
-
- rx_ready_timer = WaitTimer(1*clk_freq//1000)
- self.submodules += rx_ready_timer
- self.comb += [
- rx_ready_timer.wait.eq(~self.rx_ready),
- rx_startup_fsm.reset.eq(self.rx_reset | rx_ready_timer.done),
- ]
-
- # Ready
- self.comb += self.ready.eq(self.tx_ready & self.rx_ready)
-
- # Reset for SATA TX/RX clock domains
- self.specials += [
- AsyncResetSynchronizer(self.cd_sata_tx, ~(gtx.cplllock & mmcm_locked) | self.tx_reset),
- AsyncResetSynchronizer(self.cd_sata_rx, ~gtx.cplllock | self.rx_reset),
- ]
+++ /dev/null
-from misoclib.mem.litesata.common import *
-
-
-def ones(width):
- return 2**width-1
-
-
-class _PulseSynchronizer(PulseSynchronizer):
- def __init__(self, i, idomain, o, odomain):
- PulseSynchronizer.__init__(self, idomain, odomain)
- self.comb += [
- self.i.eq(i),
- o.eq(self.o)
- ]
-
-
-class _RisingEdge(Module):
- def __init__(self, i, o):
- i_d = Signal()
- self.sync += i_d.eq(i)
- self.comb += o.eq(i & ~i_d)
-
-
-class _LowPassFilter(Module):
- def __init__(self, i, o, cycles):
- i_d = Signal()
- self.submodules.timer = WaitTimer(cycles)
- self.sync += [
- i_d.eq(i),
- If(self.timer.done,
- o.eq(i_d)
- )
- ]
- self.comb += self.timer.wait.eq(i == i_d)
-
-
-class K7LiteSATAPHYTRX(Module):
- def __init__(self, pads, revision):
- # Common signals
-
- # control
- self.tx_idle = Signal() #i
-
- self.tx_cominit_stb = Signal() #i
- self.tx_cominit_ack = Signal() #o
- self.tx_comwake_stb = Signal() #i
- self.tx_comwake_ack = Signal() #o
-
- self.rx_idle = Signal() #o
- self.rx_align = Signal() #i
-
- self.rx_cominit_stb = Signal() #o
- self.rx_comwake_stb = Signal() #o
-
- # datapath
- self.sink = Sink(phy_description(16))
- self.source = Source(phy_description(16))
-
- # K7 specific signals
- # Channel - Ref Clock Ports
- self.gtrefclk0 = Signal()
-
- # Channel PLL
- self.cplllock = Signal()
- self.cpllreset = Signal()
-
- # Receive Ports
- self.rxuserrdy = Signal()
-
- # Receive Ports - 8b10b Decoder
- self.rxcharisk = Signal(2)
-
- # Receive Ports - RX Data Path interface
- self.gtrxreset = Signal()
- self.rxdata = Signal(16)
- self.rxoutclk = Signal()
- self.rxusrclk = Signal()
- self.rxusrclk2 = Signal()
-
- # Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR
- self.rxelecidle = Signal()
-
- # Receive Ports - RX PLL Ports
- self.rxresetdone = Signal()
- self.rxdlyreset = Signal()
- self.rxdlyresetdone = Signal()
-
- # Receive Ports - RX Ports for SATA
- self.rxcominitdet = Signal()
- self.rxcomwakedet = Signal()
-
- # Transmit Ports
- self.txuserrdy = Signal()
-
- # Transmit Ports - 8b10b Encoder Control Ports
- self.txcharisk = Signal(2)
-
- # Transmit Ports - TX Data Path interface
- self.gttxreset = Signal()
- self.txdata = Signal(16)
- self.txoutclk = Signal()
- self.txusrclk = Signal()
- self.txusrclk2 = Signal()
-
- # Transmit Ports - TX PLL Ports
- self.txresetdone = Signal()
- self.txdlyreset = Signal()
- self.txdlyresetdone = Signal()
-
- # Transmit Ports - TX Ports for PCI Express
- self.txelecidle = Signal(reset=1)
-
- # Transmit Ports - TX Ports for SATA
- self.txcomfinish = Signal()
- self.txcominit = Signal()
- self.txcomwake = Signal()
-
- # Config at startup
- div_config = {
- "sata_gen1": 4,
- "sata_gen2": 2,
- "sata_gen3": 1
- }
- rxout_div = div_config[revision]
- txout_div = div_config[revision]
-
- cdr_config = {
- "sata_gen1": 0x0380008BFF40100008,
- "sata_gen2": 0x0388008BFF40200008,
- "sata_gen3": 0x0380008BFF10200010
- }
- rxcdr_cfg = cdr_config[revision]
-
- # Specific / Generic signals encoding/decoding
- self.comb += [
- self.txelecidle.eq(self.tx_idle),
- self.tx_cominit_ack.eq(self.tx_cominit_stb & self.txcomfinish),
- self.tx_comwake_ack.eq(self.tx_comwake_stb & self.txcomfinish),
- self.rx_idle.eq(self.rxelecidle),
- self.rx_cominit_stb.eq(self.rxcominitdet),
- self.rx_comwake_stb.eq(self.rxcomwakedet),
- ]
- self.submodules += [
- _RisingEdge(self.tx_cominit_stb, self.txcominit),
- _RisingEdge(self.tx_comwake_stb, self.txcomwake),
- ]
-
- self.comb += [
- self.txcharisk.eq(self.sink.charisk),
- self.txdata.eq(self.sink.data),
- self.sink.ack.eq(1),
-
- self.source.stb.eq(1),
- self.source.charisk.eq(self.rxcharisk),
- self.source.data.eq(self.rxdata)
- ]
-
- # Internals and clock domain crossing
- # sys_clk --> sata_tx clk
- txuserrdy = Signal()
- txelecidle = Signal(reset=1)
- txcominit = Signal()
- txcomwake = Signal()
- txdlyreset = Signal()
- txdlyresetdone = Signal()
- gttxreset = Signal()
-
- self.specials += [
- MultiReg(self.txuserrdy, txuserrdy, "sata_tx"),
- MultiReg(self.txelecidle, txelecidle, "sata_tx"),
- MultiReg(self.gttxreset, gttxreset, "sata_tx"),
- ]
- self.submodules += [
- _PulseSynchronizer(self.txcominit, "sys", txcominit, "sata_tx"),
- _PulseSynchronizer(self.txcomwake, "sys", txcomwake, "sata_tx"),
- _PulseSynchronizer(self.txdlyreset, "sys", txdlyreset, "sata_tx"),
- ]
-
- # sata_tx clk --> sys clk
- txresetdone = Signal()
- txcomfinish = Signal()
-
- self.specials += [
- MultiReg(txresetdone, self.txresetdone, "sys"),
- MultiReg(txdlyresetdone, self.txdlyresetdone, "sys"),
- ]
-
- self.submodules += [
- _PulseSynchronizer(txcomfinish, "sata_tx", self.txcomfinish, "sys"),
- ]
-
- # sys clk --> sata_rx clk
- rxuserrdy = Signal()
- rxdlyreset = Signal()
-
- self.specials += [
- MultiReg(self.rxuserrdy, rxuserrdy, "sata_rx"),
- ]
-
- self.submodules += [
- _PulseSynchronizer(self.rxdlyreset, "sys", rxdlyreset, "sata_rx"),
- ]
-
- # sata_rx clk --> sys clk
- rxelecidle = Signal()
- rxelecidle_i = Signal()
- rxresetdone = Signal()
- rxcominitdet = Signal()
- rxcomwakedet = Signal()
- rxratedone = Signal()
- rxdlyresetdone = Signal()
-
- self.specials += [
- MultiReg(rxelecidle, rxelecidle_i, "sys"),
- MultiReg(rxresetdone, self.rxresetdone, "sys"),
- MultiReg(rxcominitdet, self.rxcominitdet, "sys"),
- MultiReg(rxcomwakedet, self.rxcomwakedet, "sys"),
- MultiReg(rxdlyresetdone, self.rxdlyresetdone, "sys"),
- ]
-
- rxelecidle_filter = _LowPassFilter(rxelecidle_i, self.rxelecidle, 256)
- self.submodules += rxelecidle_filter
-
- # QPLL input clock
- self.qpllclk = Signal()
- self.qpllrefclk = Signal()
-
- # Instance
- gtxe2_channel_parameters = {
- # Simulation-Only Attributes
- "p_SIM_RECEIVER_DETECT_PASS": "TRUE",
- "p_SIM_TX_EIDLE_DRIVE_LEVEL": "X",
- "p_SIM_RESET_SPEEDUP": "TRUE",
- "p_SIM_CPLLREFCLK_SEL": 0b001,
- "p_SIM_VERSION": "4.0",
-
- # RX Byte and Word Alignment Attributes
- "p_ALIGN_COMMA_DOUBLE": "FALSE",
- "p_ALIGN_COMMA_ENABLE": ones(10),
- "p_ALIGN_COMMA_WORD": 1,
- "p_ALIGN_MCOMMA_DET": "TRUE",
- "p_ALIGN_MCOMMA_VALUE": 0b1010000011,
- "p_ALIGN_PCOMMA_DET": "TRUE",
- "p_ALIGN_PCOMMA_VALUE": 0b0101111100,
- "p_SHOW_REALIGN_COMMA": "FALSE",
- "p_RXSLIDE_AUTO_WAIT": 7,
- "p_RXSLIDE_MODE": "PCS",
- "p_RX_SIG_VALID_DLY": 10,
-
- # RX 8B/10B Decoder Attributes
- "p_RX_DISPERR_SEQ_MATCH": "TRUE",
- "p_DEC_MCOMMA_DETECT": "TRUE",
- "p_DEC_PCOMMA_DETECT": "TRUE",
- "p_DEC_VALID_COMMA_ONLY": "FALSE",
-
- # RX Clock Correction Attributes
- "p_CBCC_DATA_SOURCE_SEL": "DECODED",
- "p_CLK_COR_SEQ_2_USE": "FALSE",
- "p_CLK_COR_KEEP_IDLE": "FALSE",
- "p_CLK_COR_MAX_LAT": 9,
- "p_CLK_COR_MIN_LAT": 7,
- "p_CLK_COR_PRECEDENCE": "TRUE",
- "p_CLK_COR_REPEAT_WAIT": 0,
- "p_CLK_COR_SEQ_LEN": 1,
- "p_CLK_COR_SEQ_1_ENABLE": ones(4),
- "p_CLK_COR_SEQ_1_1": 0b0100000000,
- "p_CLK_COR_SEQ_1_2": 0b0000000000,
- "p_CLK_COR_SEQ_1_3": 0b0000000000,
- "p_CLK_COR_SEQ_1_4": 0b0000000000,
- "p_CLK_CORRECT_USE": "FALSE",
- "p_CLK_COR_SEQ_2_ENABLE": ones(4),
- "p_CLK_COR_SEQ_2_1": 0b0100000000,
- "p_CLK_COR_SEQ_2_2": 0b0000000000,
- "p_CLK_COR_SEQ_2_3": 0b0000000000,
- "p_CLK_COR_SEQ_2_4": 0b0000000000,
-
- # RX Channel Bonding Attributes
- "p_CHAN_BOND_KEEP_ALIGN": "FALSE",
- "p_CHAN_BOND_MAX_SKEW": 1,
- "p_CHAN_BOND_SEQ_LEN": 1,
- "p_CHAN_BOND_SEQ_1_1": 0,
- "p_CHAN_BOND_SEQ_1_1": 0,
- "p_CHAN_BOND_SEQ_1_2": 0,
- "p_CHAN_BOND_SEQ_1_3": 0,
- "p_CHAN_BOND_SEQ_1_4": 0,
- "p_CHAN_BOND_SEQ_1_ENABLE": ones(4),
- "p_CHAN_BOND_SEQ_2_1": 0,
- "p_CHAN_BOND_SEQ_2_2": 0,
- "p_CHAN_BOND_SEQ_2_3": 0,
- "p_CHAN_BOND_SEQ_2_4": 0,
- "p_CHAN_BOND_SEQ_2_ENABLE": ones(4),
- "p_CHAN_BOND_SEQ_2_USE": "FALSE",
- "p_FTS_DESKEW_SEQ_ENABLE": ones(4),
- "p_FTS_LANE_DESKEW_CFG": ones(4),
- "p_FTS_LANE_DESKEW_EN": "FALSE",
-
- # RX Margin Analysis Attributes
- "p_ES_CONTROL": 0,
- "p_ES_ERRDET_EN": "FALSE",
- "p_ES_EYE_SCAN_EN": "TRUE",
- "p_ES_HORZ_OFFSET": 0,
- "p_ES_PMA_CFG": 0,
- "p_ES_PRESCALE": 0,
- "p_ES_QUALIFIER": 0,
- "p_ES_QUAL_MASK": 0,
- "p_ES_SDATA_MASK": 0,
- "p_ES_VERT_OFFSET": 0,
-
- # FPGA RX Interface Attributes
- "p_RX_DATA_WIDTH": 20,
-
- # PMA Attributes
- "p_OUTREFCLK_SEL_INV": 0b11,
- "p_PMA_RSV": 0x00018480,
- "p_PMA_RSV2": 0x2050,
- "p_PMA_RSV3": 0,
- "p_PMA_RSV4": 0,
- "p_RX_BIAS_CFG": 0b100,
- "p_DMONITOR_CFG": 0xA00,
- "p_RX_CM_SEL": 0b11,
- "p_RX_CM_TRIM": 0b010,
- "p_RX_DEBUG_CFG": 0,
- "p_RX_OS_CFG": 0b10000000,
- "p_TERM_RCAL_CFG": 0b10000,
- "p_TERM_RCAL_OVRD": 0,
- "p_TST_RSV": 0,
- "p_RX_CLK25_DIV": 6,
- "p_TX_CLK25_DIV": 6,
- "p_UCODEER_CLR": 0,
-
- # PCI Express Attributes
- "p_PCS_PCIE_EN": "FALSE",
-
- # PCS Attributes
- "p_PCS_RSVD_ATTR": 0x100,
-
- # RX Buffer Attributes
- "p_RXBUF_ADDR_MODE": "FAST",
- "p_RXBUF_EIDLE_HI_CNT": 0b1000,
- "p_RXBUF_EIDLE_LO_CNT": 0b0000,
- "p_RXBUF_EN": "FALSE",
- "p_RX_BUFFER_CFG": 0,
- "p_RXBUF_RESET_ON_CB_CHANGE": "TRUE",
- "p_RXBUF_RESET_ON_COMMAALIGN": "FALSE",
- "p_RXBUF_RESET_ON_EIDLE": "FALSE",
- "p_RXBUF_RESET_ON_RATE_CHANGE": "TRUE",
- "p_RXBUFRESET_TIME": 1,
- "p_RXBUF_THRESH_OVFLW": 61,
- "p_RXBUF_THRESH_OVRD": "FALSE",
- "p_RXBUF_THRESH_UNDFLW": 4,
- "p_RXDLY_CFG": 0x1f,
- "p_RXDLY_LCFG": 0x30,
- "p_RXDLY_TAP_CFG": 0,
- "p_RXPH_CFG": 0,
- "p_RXPHDLY_CFG": 0x084020,
- "p_RXPH_MONITOR_SEL": 0,
- "p_RX_XCLK_SEL": "RXUSR",
- "p_RX_DDI_SEL": 0,
- "p_RX_DEFER_RESET_BUF_EN": "TRUE",
-
- # CDR Attributes
- "p_RXCDR_CFG": rxcdr_cfg,
- "p_RXCDR_FR_RESET_ON_EIDLE": 0,
- "p_RXCDR_HOLD_DURING_EIDLE": 0,
- "p_RXCDR_PH_RESET_ON_EIDLE": 0,
- "p_RXCDR_LOCK_CFG": 0b010101,
-
- # RX Initialization and Reset Attributes
- "p_RXCDRFREQRESET_TIME": 1,
- "p_RXCDRPHRESET_TIME": 1,
- "p_RXISCANRESET_TIME": 1,
- "p_RXPCSRESET_TIME": 1,
- "p_RXPMARESET_TIME": 3,
-
- # RX OOB Signaling Attributes
- "p_RXOOB_CFG": 0b0000110,
-
- # RX Gearbox Attributes
- "p_RXGEARBOX_EN": "FALSE",
- "p_GEARBOX_MODE": 0,
-
- # PRBS Detection Attribute
- "p_RXPRBS_ERR_LOOPBACK": 0,
-
- # Power-Down Attributes
- "p_PD_TRANS_TIME_FROM_P2": 0x03c,
- "p_PD_TRANS_TIME_NONE_P2": 0x3c,
- "p_PD_TRANS_TIME_TO_P2": 0x64,
-
- # RX OOB Signaling Attributes
- "p_SAS_MAX_COM": 64,
- "p_SAS_MIN_COM": 36,
- "p_SATA_BURST_SEQ_LEN": 0b0101,
- "p_SATA_BURST_VAL": 0b100,
- "p_SATA_EIDLE_VAL": 0b100,
- "p_SATA_MAX_BURST": 8,
- "p_SATA_MAX_INIT": 21,
- "p_SATA_MAX_WAKE": 7,
- "p_SATA_MIN_BURST": 4,
- "p_SATA_MIN_INIT": 12,
- "p_SATA_MIN_WAKE": 4,
-
- # RX Fabric Clock Output Control Attributes
- "p_TRANS_TIME_RATE": 0x0e,
-
- # TX Buffer Attributes
- "p_TXBUF_EN": "FALSE",
- "p_TXBUF_RESET_ON_RATE_CHANGE": "FALSE",
- "p_TXDLY_CFG": 0x1f,
- "p_TXDLY_LCFG": 0x030,
- "p_TXDLY_TAP_CFG": 0,
- "p_TXPH_CFG": 0x0780,
- "p_TXPHDLY_CFG": 0x084020,
- "p_TXPH_MONITOR_SEL": 0,
- "p_TX_XCLK_SEL": "TXUSR",
-
- # FPGA TX Interface Attributes
- "p_TX_DATA_WIDTH": 20,
-
- # TX Configurable Driver Attributes
- "p_TX_DEEMPH0": 0,
- "p_TX_DEEMPH1": 0,
- "p_TX_EIDLE_ASSERT_DELAY": 0b110,
- "p_TX_EIDLE_DEASSERT_DELAY": 0b100,
- "p_TX_LOOPBACK_DRIVE_HIZ": "FALSE",
- "p_TX_MAINCURSOR_SEL": 0,
- "p_TX_DRIVE_MODE": "DIRECT",
- "p_TX_MARGIN_FULL_0": 0b1001110,
- "p_TX_MARGIN_FULL_1": 0b1001001,
- "p_TX_MARGIN_FULL_2": 0b1000101,
- "p_TX_MARGIN_FULL_3": 0b1000010,
- "p_TX_MARGIN_FULL_4": 0b1000000,
- "p_TX_MARGIN_LOW_0": 0b1000110,
- "p_TX_MARGIN_LOW_1": 0b1000100,
- "p_TX_MARGIN_LOW_2": 0b1000010,
- "p_TX_MARGIN_LOW_3": 0b1000000,
- "p_TX_MARGIN_LOW_4": 0b1000000,
-
- # TX Gearbox Attributes
- "p_TXGEARBOX_EN": "FALSE",
-
- # TX Initialization and Reset Attributes
- "p_TXPCSRESET_TIME": 1,
- "p_TXPMARESET_TIME": 1,
-
- # TX Receiver Detection Attributes
- "p_TX_RXDETECT_CFG": 0x1832,
- "p_TX_RXDETECT_REF": 0b100,
-
- # CPLL Attributes
- "p_CPLL_CFG": 0xBC07DC,
- "p_CPLL_FBDIV": 4,
- "p_CPLL_FBDIV_45": 5,
- "p_CPLL_INIT_CFG": 0x00001e,
- "p_CPLL_LOCK_CFG": 0x01e8,
- "p_CPLL_REFCLK_DIV": 1,
- "p_RXOUT_DIV": rxout_div,
- "p_TXOUT_DIV": txout_div,
- "p_SATA_CPLL_CFG": "VCO_3000MHZ",
-
- # RX Initialization and Reset Attributes
- "p_RXDFELPMRESET_TIME": 0b0001111,
-
- # RX Equalizer Attributes
- "p_RXLPM_HF_CFG": 0b00000011110000,
- "p_RXLPM_LF_CFG": 0b00000011110000,
- "p_RX_DFE_GAIN_CFG": 0x020fea,
- "p_RX_DFE_H2_CFG": 0b000000000000,
- "p_RX_DFE_H3_CFG": 0b000001000000,
- "p_RX_DFE_H4_CFG": 0b00011110000,
- "p_RX_DFE_H5_CFG": 0b00011100000,
- "p_RX_DFE_KL_CFG": 0b0000011111110,
- "p_RX_DFE_LPM_CFG": 0x0954,
- "p_RX_DFE_LPM_HOLD_DURING_EIDLE": 1,
- "p_RX_DFE_UT_CFG": 0b10001111000000000,
- "p_RX_DFE_VP_CFG": 0b00011111100000011,
-
- # Power-Down Attributes
- "p_RX_CLKMUX_PD": 1,
- "p_TX_CLKMUX_PD": 1,
-
- # FPGA RX Interface Attribute
- "p_RX_INT_DATAWIDTH": 0,
-
- # FPGA TX Interface Attribute
- "p_TX_INT_DATAWIDTH": 0,
-
- # TX Configurable Driver Attributes
- "p_TX_QPI_STATUS_EN": 0,
-
- # RX Equalizer Attributes
- "p_RX_DFE_KL_CFG2": 0b00110011000100000001100000001100,
- "p_RX_DFE_XYD_CFG": 0b0000000000000,
-
- # TX Configurable Driver Attributes
- "p_TX_PREDRIVER_MODE": 0,
- }
-
- self.specials += \
- Instance("GTXE2_CHANNEL",
- # CPLL Ports
- #o_CPLLFBCLKLOST=,
- o_CPLLLOCK=self.cplllock,
- i_CPLLLOCKDETCLK=0,
- i_CPLLLOCKEN=1,
- i_CPLLPD=0,
- #o_CPLLREFCLKLOST=0,
- i_CPLLREFCLKSEL=0b001,
- i_CPLLRESET=self.cpllreset,
- i_GTRSVD=0,
- i_PCSRSVDIN=0,
- i_PCSRSVDIN2=0,
- i_PMARSVDIN=0,
- i_PMARSVDIN2=0,
- i_TSTIN=ones(20),
- #o_TSTOUT=,
-
- # Channel
- i_CLKRSVD=0,
-
- # Channel - Clocking Ports
- i_GTGREFCLK=0,
- i_GTNORTHREFCLK0=0,
- i_GTNORTHREFCLK1=0,
- i_GTREFCLK0=self.gtrefclk0,
- i_GTREFCLK1=0,
- i_GTSOUTHREFCLK0=0,
- i_GTSOUTHREFCLK1=0,
-
- # Channel - DRP Ports
- i_DRPADDR=0,
- i_DRPCLK=0,
- i_DRPDI=0,
- #o_DRPDO=,
- i_DRPEN=0,
- #o_DRPRDY=,
- i_DRPWE=0,
-
- # Clocking Ports
- #o_GTREFCLKMONITOR=,
- i_QPLLCLK=self.qpllclk,
- i_QPLLREFCLK=self.qpllrefclk,
- i_RXSYSCLKSEL=0b00,
- i_TXSYSCLKSEL=0b00,
-
- # Digital Monitor Ports
- #o_DMONITOROUT=,
-
- # FPGA TX Interface Datapath Configuration
- i_TX8B10BEN=1,
-
- # Loopback Ports
- i_LOOPBACK=0,
-
- # PCI Express Ports
- #o_PHYSTATUS=,
- i_RXRATE=0,
- #o_RXVALID=,
-
- # Power-Down Ports
- i_RXPD=0b00,
- i_TXPD=0b00,
-
- # RX 8B/10B Decoder Ports
- i_SETERRSTATUS=0,
-
- # RX Initialization and Reset Ports
- i_EYESCANRESET=0,
- i_RXUSERRDY=rxuserrdy,
-
- # RX Margin Analysis Ports
- #o_EYESCANDATAERROR=,
- i_EYESCANMODE=0,
- i_EYESCANTRIGGER=0,
-
- # Receive Ports - CDR Ports
- i_RXCDRFREQRESET=0,
- i_RXCDRHOLD=self.rxelecidle,
- #o_RXCDRLOCK=,
- i_RXCDROVRDEN=0,
- i_RXCDRRESET=0,
- i_RXCDRRESETRSV=0,
-
- # Receive Ports - Clock Correction Ports
- #o_RXCLKCORCNT=,
-
- # Receive Ports - FPGA RX Interface Datapath Configuration
- i_RX8B10BEN=1,
-
- # Receive Ports - FPGA RX Interface Ports
- i_RXUSRCLK=self.rxusrclk,
- i_RXUSRCLK2=self.rxusrclk2,
-
- # Receive Ports - FPGA RX interface Ports
- o_RXDATA=self.rxdata,
-
- # Receive Ports - Pattern Checker Ports
- #o_RXPRBSERR=,
- i_RXPRBSSEL=0,
-
- # Receive Ports - Pattern Checker ports
- i_RXPRBSCNTRESET=0,
-
- # Receive Ports - RX Equalizer Ports
- i_RXDFEXYDEN=1,
- i_RXDFEXYDHOLD=0,
- i_RXDFEXYDOVRDEN=0,
-
- # Receive Ports - RX 8B/10B Decoder Ports
- #o_RXDISPERR=,
- #o_RXNOTINTABLE=,
-
- # Receive Ports - RX AFE
- i_GTXRXP=pads.rxp,
- i_GTXRXN=pads.rxn,
-
- # Receive Ports - RX Buffer Bypass Ports
- i_RXBUFRESET=0,
- #o_RXBUFSTATUS=,
- i_RXDDIEN=1,
- i_RXDLYBYPASS=0,
- i_RXDLYEN=0,
- i_RXDLYOVRDEN=0,
- i_RXDLYSRESET=rxdlyreset,
- o_RXDLYSRESETDONE=rxdlyresetdone,
- i_RXPHALIGN=0,
- #o_RXPHALIGNDONE=,
- i_RXPHALIGNEN=0,
- i_RXPHDLYPD=0,
- i_RXPHDLYRESET=0,
- #o_RXPHMONITOR=,
- i_RXPHOVRDEN=0,
- #o_RXPHSLIPMONITOR=,
- #o_RXSTATUS=,
-
- # Receive Ports - RX Byte and Word Alignment Ports
- #o_RXBYTEISALIGNED=,
- #o_RXBYTEREALIGN=,
- #o_RXCOMMADET=,
- i_RXCOMMADETEN=1,
- i_RXMCOMMAALIGNEN=1,
- i_RXPCOMMAALIGNEN=1,
-
- # Receive Ports - RX Channel Bonding Ports
- #o_RXCHANBONDSEQ=,
- i_RXCHBONDEN=0,
- i_RXCHBONDLEVEL=0,
- i_RXCHBONDMASTER=0,
- #o_RXCHBONDO=,
- i_RXCHBONDSLAVE=0,
-
- # Receive Ports - RX Channel Bonding Ports
- #o_RXCHANISALIGNED=,
- #o_RXCHANREALIGN=,
-
- # Receive Ports - RX Equalizer Ports
- i_RXDFEAGCHOLD=0,
- i_RXDFEAGCOVRDEN=0,
- i_RXDFECM1EN=0,
- i_RXDFELFHOLD=0,
- i_RXDFELFOVRDEN=0,
- i_RXDFELPMRESET=0,
- i_RXDFETAP2HOLD=0,
- i_RXDFETAP2OVRDEN=0,
- i_RXDFETAP3HOLD=0,
- i_RXDFETAP3OVRDEN=0,
- i_RXDFETAP4HOLD=0,
- i_RXDFETAP4OVRDEN=0,
- i_RXDFETAP5HOLD=0,
- i_RXDFETAP5OVRDEN=0,
- i_RXDFEUTHOLD=0,
- i_RXDFEUTOVRDEN=0,
- i_RXDFEVPHOLD=0,
- i_RXDFEVPOVRDEN=0,
- i_RXDFEVSEN=0,
- i_RXLPMLFKLOVRDEN=0,
- #o_RXMONITOROUT=,
- i_RXMONITORSEL=0b00,
- i_RXOSHOLD=0,
- i_RXOSOVRDEN=0,
-
- # Receive Ports - RX Equilizer Ports
- i_RXLPMHFHOLD=0,
- i_RXLPMHFOVRDEN=0,
- i_RXLPMLFHOLD=0,
-
- # Receive Ports - RX Fabric ClocK Output Control Ports
- #o_RXRATEDONE=,
-
- # Receive Ports - RX Fabric Output Control Ports
- o_RXOUTCLK=self.rxoutclk,
- #o_RXOUTCLKFABRIC=,
- #o_RXOUTCLKPCS=,
- i_RXOUTCLKSEL=0b010,
-
- # Receive Ports - RX Gearbox Ports
- #o_RXDATAVALID=,
- #o_RXHEADER=,
- #o_RXHEADERVALID=,
- #o_RXSTARTOFSEQ=,
-
- # Receive Ports - RX Gearbox Ports
- i_RXGEARBOXSLIP=0,
-
- # Receive Ports - RX Initialization and Reset Ports
- i_GTRXRESET=self.gtrxreset,
- i_RXOOBRESET=0,
- i_RXPCSRESET=0,
- i_RXPMARESET=0,
-
- # Receive Ports - RX Margin Analysis ports
- i_RXLPMEN=0,
-
- # Receive Ports - RX OOB Signaling ports
- #o_RXCOMSASDET=,
- o_RXCOMWAKEDET=rxcomwakedet,
-
- # Receive Ports - RX OOB Signaling ports
- o_RXCOMINITDET=rxcominitdet,
-
- # Receive Ports - RX OOB signalling Ports
- o_RXELECIDLE=rxelecidle,
- i_RXELECIDLEMODE=0b00,
-
- # Receive Ports - RX Polarity Control Ports
- i_RXPOLARITY=0,
-
- # Receive Ports - RX gearbox ports
- i_RXSLIDE=0,
-
- # Receive Ports - RX8B/10B Decoder Ports
- #o_RXCHARISCOMMA=,
- o_RXCHARISK=self.rxcharisk,
-
- # Receive Ports - Rx Channel Bonding Ports
- i_RXCHBONDI=0,
-
- # Receive Ports -RX Initialization and Reset Ports
- o_RXRESETDONE=rxresetdone,
-
- # Rx AFE Ports
- i_RXQPIEN=0,
- #o_RXQPISENN=,
- #o_RXQPISENP=,
-
- # TX Buffer Bypass Ports
- i_TXPHDLYTSTCLK=0,
-
- # TX Configurable Driver Ports
- i_TXPOSTCURSOR=0,
- i_TXPOSTCURSORINV=0,
- i_TXPRECURSOR=0,
- i_TXPRECURSORINV=0,
- i_TXQPIBIASEN=0,
- i_TXQPISTRONGPDOWN=0,
- i_TXQPIWEAKPUP=0,
-
- # TX Initialization and Reset Ports
- i_CFGRESET=0,
- i_GTTXRESET=gttxreset,
- #o_PCSRSVDOUT=,
- i_TXUSERRDY=txuserrdy,
-
- # Transceiver Reset Mode Operation
- i_GTRESETSEL=0,
- i_RESETOVRD=0,
-
- # Transmit Ports - 8b10b Encoder Control Ports
- i_TXCHARDISPMODE=0,
- i_TXCHARDISPVAL=0,
-
- # Transmit Ports - FPGA TX Interface Ports
- i_TXUSRCLK=self.txusrclk,
- i_TXUSRCLK2=self.txusrclk2,
-
- # Transmit Ports - PCI Express Ports
- i_TXELECIDLE=txelecidle,
- i_TXMARGIN=0,
- i_TXRATE=0,
- i_TXSWING=0,
-
- # Transmit Ports - Pattern Generator Ports
- i_TXPRBSFORCEERR=0,
-
- # Transmit Ports - TX Buffer Bypass Ports
- i_TXDLYBYPASS=0,
- i_TXDLYEN=0,
- i_TXDLYHOLD=0,
- i_TXDLYOVRDEN=0,
- i_TXDLYSRESET=txdlyreset,
- o_TXDLYSRESETDONE=txdlyresetdone,
- i_TXDLYUPDOWN=0,
- i_TXPHALIGN=0,
- #o_TXPHALIGNDONE=txphaligndone,
- i_TXPHALIGNEN=0,
- i_TXPHDLYPD=0,
- i_TXPHDLYRESET=0,
- i_TXPHINIT=0,
- #o_TXPHINITDONE=,
- i_TXPHOVRDEN=0,
-
- # Transmit Ports - TX Buffer Ports
- #o_TXBUFSTATUS=,
-
- # Transmit Ports - TX Configurable Driver Ports
- i_TXBUFDIFFCTRL=0b100,
- i_TXDEEMPH=0,
- i_TXDIFFCTRL=0b1000,
- i_TXDIFFPD=0,
- i_TXINHIBIT=0,
- i_TXMAINCURSOR=0,
- i_TXPISOPD=0,
-
- # Transmit Ports - TX Data Path interface
- i_TXDATA=self.txdata,
-
- # Transmit Ports - TX Driver and OOB signaling
- o_GTXTXP=pads.txp,
- o_GTXTXN=pads.txn,
-
- # Transmit Ports - TX Fabric Clock Output Control Ports
- o_TXOUTCLK=self.txoutclk,
- #o_TXOUTCLKFABRIC=,
- #o_TXOUTCLKPCS=,
- i_TXOUTCLKSEL=0b11,
- #o_TXRATEDONE=,
- # Transmit Ports - TX Gearbox Ports
- i_TXCHARISK=self.txcharisk,
- #o_TXGEARBOXREADY=,
- i_TXHEADER=0,
- i_TXSEQUENCE=0,
- i_TXSTARTSEQ=0,
-
- # Transmit Ports - TX Initialization and Reset Ports
- i_TXPCSRESET=0,
- i_TXPMARESET=0,
- o_TXRESETDONE=txresetdone,
-
- # Transmit Ports - TX OOB signalling Ports
- o_TXCOMFINISH=txcomfinish,
- i_TXCOMINIT=txcominit,
- i_TXCOMSAS=0,
- i_TXCOMWAKE=txcomwake,
- i_TXPDELECIDLEMODE=0,
-
- # Transmit Ports - TX Polarity Control Ports
- i_TXPOLARITY=0,
-
- # Transmit Ports - TX Receiver Detection Ports
- i_TXDETECTRX=0,
-
- # Transmit Ports - TX8b/10b Encoder Ports
- i_TX8B10BBYPASS=0,
-
- # Transmit Ports - pattern Generator Ports
- i_TXPRBSSEL=0,
-
- # Tx Configurable Driver Ports
- #o_TXQPISENN=,
- #o_TXQPISENP=,
-
- **gtxe2_channel_parameters
- )
+++ /dev/null
-MSCDIR = ../../../../
-PYTHON = python3
-
-CMD = PYTHONPATH=$(PYTHONPATH):$(MSCDIR) $(PYTHON)
-
-CC=gcc
-CFLAGS =-Wall -O0
-
-phy_datapath_tb:
- $(CMD) phy_datapath_tb.py
-
-crc_tb:
- $(CC) $(CFLAGS) $(INC) -o crc crc.c
- $(CMD) crc_tb.py
-
-scrambler_tb: scrambler
- $(CMD) scrambler_tb.py
-
-cont_tb:
- $(CMD) cont_tb.py
-
-link_tb:
- $(CMD) link_tb.py
-
-command_tb:
- $(CMD) command_tb.py
-
-bist_tb: scrambler
- $(CMD) bist_tb.py
-
-striping_tb:
- $(CMD) striping_tb.py
-
-mirroring_tb:
- $(CMD) mirroring_tb.py
-
-scrambler: scrambler.c
- $(CC) $(CFLAGS) $(INC) -o $@ $<
-
-clean:
- rm -f crc scrambler *.vcd
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.core import LiteSATACore
-from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
-from misoclib.mem.litesata.frontend.bist import LiteSATABISTGenerator, LiteSATABISTChecker
-
-from misoclib.mem.litesata.test.common import *
-from misoclib.mem.litesata.test.model.hdd import *
-
-
-class TB(Module):
- def __init__(self):
- self.submodules.hdd = HDD(
- link_debug=False, link_random_level=0,
- transport_debug=False, transport_loopback=False,
- hdd_debug=True)
- self.submodules.core = LiteSATACore(self.hdd.phy)
- self.submodules.crossbar = LiteSATACrossbar(self.core)
- self.submodules.generator = LiteSATABISTGenerator(self.crossbar.get_port())
- self.submodules.checker = LiteSATABISTChecker(self.crossbar.get_port())
-
- def gen_simulation(self, selfp):
- hdd = self.hdd
- hdd.malloc(0, 64)
- sector = 0
- count = 17
- generator = selfp.generator
- checker = selfp.checker
- while True:
- # write data
- generator.sector = sector
- generator.count = count
- generator.start = 1
- yield
- generator.start = 0
- yield
- while generator.done == 0:
- yield
-
- # verify data
- checker.sector = sector
- checker.count = count
- checker.start = 1
- yield
- checker.start = 0
- yield
- while checker.done == 0:
- yield
- print("errors {}".format(checker.errors))
-
- # prepare next iteration
- sector += 1
- count = max((count + 1)%8, 1)
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=8192*2, vcd_name="my.vcd", keep_files=True)
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.core import LiteSATACore
-
-from misoclib.mem.litesata.test.common import *
-from misoclib.mem.litesata.test.model.hdd import *
-
-
-class CommandTXPacket(list):
- def __init__(self, write=0, read=0, sector=0, count=0, data=[]):
- self.ongoing = False
- self.done = False
- self.write = write
- self.read = read
- self.sector = sector
- self.count = count
- for d in data:
- self.append(d)
-
-
-class CommandStreamer(PacketStreamer):
- def __init__(self):
- PacketStreamer.__init__(self, command_tx_description(32), CommandTXPacket)
-
- def do_simulation(self, selfp):
- PacketStreamer.do_simulation(self, selfp)
- selfp.source.write = self.packet.write
- selfp.source.read = self.packet.read
- selfp.source.sector = self.packet.sector
- selfp.source.count = self.packet.count
-
-
-class CommandRXPacket(list):
- def __init__(self):
- self.ongoing = False
- self.done = False
- self.write = 0
- self.read = 0
- self.failed = 0
-
-
-class CommandLogger(PacketLogger):
- def __init__(self):
- PacketLogger.__init__(self, command_rx_description(32), CommandRXPacket)
-
- def do_simulation(self, selfp):
- selfp.sink.ack = 1
- if selfp.sink.stb == 1 and selfp.sink.sop == 1:
- self.packet = CommandRXPacket()
- self.packet.write = selfp.sink.write
- self.packet.read = selfp.sink.read
- self.packet.failed = selfp.sink.failed
- self.packet.append(selfp.sink.data)
- elif selfp.sink.stb:
- self.packet.append(selfp.sink.data)
- if selfp.sink.stb == 1 and selfp.sink.eop == 1:
- self.packet.done = True
-
-
-class TB(Module):
- def __init__(self):
- self.submodules.hdd = HDD(
- link_debug=False, link_random_level=50,
- transport_debug=False, transport_loopback=False,
- hdd_debug=True)
- self.submodules.core = LiteSATACore(self.hdd.phy, buffer_depth=512)
-
- self.submodules.streamer = CommandStreamer()
- self.submodules.streamer_randomizer = Randomizer(command_tx_description(32), level=50)
-
- self.submodules.logger = CommandLogger()
- self.submodules.logger_randomizer = Randomizer(command_rx_description(32), level=50)
-
- self.submodules.pipeline = Pipeline(
- self.streamer,
- self.streamer_randomizer,
- self.core,
- self.logger_randomizer,
- self.logger
- )
-
- def gen_simulation(self, selfp):
- hdd = self.hdd
- hdd.malloc(0, 64)
- write_data = [i for i in range(sectors2dwords(2))]
- write_len = dwords2sectors(len(write_data))
- write_packet = CommandTXPacket(write=1, sector=2, count=write_len, data=write_data)
- yield from self.streamer.send(write_packet)
- yield from self.logger.receive()
- read_packet = CommandTXPacket(read=1, sector=2, count=write_len)
- yield from self.streamer.send(read_packet)
- yield from self.logger.receive()
- read_data = self.logger.packet
-
- # check results
- s, l, e = check(write_data, read_data)
- print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
+++ /dev/null
-import random
-import copy
-
-from migen.sim.generic import run_simulation
-
-from misoclib.mem.litesata.common import *
-
-def print_with_prefix(s, prefix=""):
- if not isinstance(s, str):
- s = s.__repr__()
- s = s.split("\n")
- for l in s:
- print(prefix + l)
-
-
-def seed_to_data(seed, random=True):
- if random:
- return (seed * 0x31415979 + 1) & 0xffffffff
- else:
- return seed
-
-
-def check(p1, p2):
- p1 = copy.deepcopy(p1)
- p2 = copy.deepcopy(p2)
- if isinstance(p1, int):
- return 0, 1, int(p1 != p2)
- else:
- if len(p1) >= len(p2):
- ref, res = p1, p2
- else:
- ref, res = p2, p1
- shift = 0
- while((ref[0] != res[0]) and (len(res) > 1)):
- res.pop(0)
- shift += 1
- length = min(len(ref), len(res))
- errors = 0
- for i in range(length):
- if ref.pop(0) != res.pop(0):
- errors += 1
- return shift, length, errors
-
-
-def randn(max_n):
- return random.randint(0, max_n-1)
-
-
-class PacketStreamer(Module):
- def __init__(self, description, packet_class):
- self.source = Source(description)
-
- # # #
-
- self.packets = []
- self.packet = packet_class()
- self.packet.done = 1
-
- self.source_data = 0
-
- def send(self, packet, blocking=True):
- packet = copy.deepcopy(packet)
- self.packets.append(packet)
- if blocking:
- while packet.done == 0:
- yield
-
- def do_simulation(self, selfp):
- if len(self.packets) and self.packet.done:
- self.packet = self.packets.pop(0)
- if not self.packet.ongoing and not self.packet.done:
- selfp.source.stb = 1
- if self.source.description.packetized:
- selfp.source.sop = 1
- if len(self.packet) > 0:
- self.source_data = self.packet.pop(0)
- if hasattr(selfp.source, "data"):
- selfp.source.data = self.source_data
- else:
- selfp.source.d = self.source_data
- self.packet.ongoing = True
- elif selfp.source.stb == 1 and selfp.source.ack == 1:
- if self.source.description.packetized:
- selfp.source.sop = 0
- selfp.source.eop = (len(self.packet) == 1)
- if len(self.packet) > 0:
- selfp.source.stb = 1
- self.source_data = self.packet.pop(0)
- if hasattr(selfp.source, "data"):
- selfp.source.data = self.source_data
- else:
- selfp.source.d = self.source_data
- else:
- self.packet.done = 1
- selfp.source.stb = 0
-
-
-class PacketLogger(Module):
- def __init__(self, description, packet_class):
- self.sink = Sink(description)
-
- # # #
-
- self.packet_class = packet_class
- self.packet = packet_class()
-
- def receive(self, length=None):
- self.packet.done = 0
- if length is None:
- while self.packet.done == 0:
- yield
- else:
- while length > len(self.packet):
- yield
-
- def do_simulation(self, selfp):
- selfp.sink.ack = 1
- if self.sink.description.packetized:
- if selfp.sink.stb == 1 and selfp.sink.sop == 1:
- self.packet = self.packet_class()
- if selfp.sink.stb:
- if hasattr(selfp.sink, "data"):
- self.packet.append(selfp.sink.data)
- else:
- self.packet.append(selfp.sink.d)
- if self.sink.description.packetized:
- if selfp.sink.stb == 1 and selfp.sink.eop == 1:
- self.packet.done = True
-
-
-class Randomizer(Module):
- def __init__(self, description, level=0):
- self.level = level
-
- self.sink = Sink(description)
- self.source = Source(description)
-
- self.run = Signal()
-
- self.comb += \
- If(self.run,
- Record.connect(self.sink, self.source)
- ).Else(
- self.source.stb.eq(0),
- self.sink.ack.eq(0),
- )
-
- def do_simulation(self, selfp):
- n = randn(100)
- if n < self.level:
- selfp.run = 0
- else:
- selfp.run = 1
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.core.link.cont import LiteSATACONTInserter, LiteSATACONTRemover
-
-from misoclib.mem.litesata.test.common import *
-
-
-class ContPacket(list):
- def __init__(self, data=[]):
- self.ongoing = False
- self.done = False
- for d in data:
- self.append(d)
-
-
-class ContStreamer(PacketStreamer):
- def __init__(self):
- PacketStreamer.__init__(self, phy_description(32), ContPacket)
-
- def do_simulation(self, selfp):
- PacketStreamer.do_simulation(self, selfp)
- selfp.source.charisk = 0
- # Note: for simplicity we generate charisk by detecting
- # primitives in data
- for k, v in primitives.items():
- try:
- if self.source_data == v:
- selfp.source.charisk = 0b0001
- except:
- pass
-
-
-class ContLogger(PacketLogger):
- def __init__(self):
- PacketLogger.__init__(self, phy_description(32), ContPacket)
-
-
-class TB(Module):
- def __init__(self):
- self.submodules.streamer = ContStreamer()
- self.submodules.streamer_randomizer = Randomizer(phy_description(32), level=50)
- self.submodules.inserter = LiteSATACONTInserter(phy_description(32))
- self.submodules.remover = LiteSATACONTRemover(phy_description(32))
- self.submodules.logger_randomizer = Randomizer(phy_description(32), level=50)
- self.submodules.logger = ContLogger()
-
- self.submodules.pipeline = Pipeline(
- self.streamer,
- self.streamer_randomizer,
- self.inserter,
- self.remover,
- self.logger_randomizer,
- self.logger
- )
-
- def gen_simulation(self, selfp):
- test_packet = ContPacket([
- primitives["SYNC"],
- primitives["SYNC"],
- primitives["SYNC"],
- primitives["SYNC"],
- primitives["SYNC"],
- primitives["SYNC"],
- primitives["ALIGN"],
- primitives["ALIGN"],
- primitives["SYNC"],
- primitives["SYNC"],
- #primitives["SYNC"],
- 0x00000000,
- 0x00000001,
- 0x00000002,
- 0x00000003,
- 0x00000004,
- 0x00000005,
- 0x00000006,
- 0x00000007,
- primitives["SYNC"],
- primitives["SYNC"],
- primitives["SYNC"],
- primitives["SYNC"],
- primitives["ALIGN"],
- primitives["ALIGN"],
- primitives["SYNC"],
- primitives["SYNC"],
- primitives["SYNC"],
- primitives["SYNC"]]*4
- )
- streamer_packet = ContPacket(test_packet)
- yield from self.streamer.send(streamer_packet)
- yield from self.logger.receive(len(test_packet))
- #for d in self.logger.packet:
- # print("{:08}".format(d))
-
- # check results
- s, l, e = check(streamer_packet, self.logger.packet)
- print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
-
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)
+++ /dev/null
-// Adapted from SATA specification
-/****************************************************************************/
-/* */
-/* crc.c */
-/* */
-/* This sample code reads standard in for a sequence of 32 bit values */
-/* formatted in hexadecimal with a leading "0x" (e.g. 0xDEADBEEF). The */
-/* code calculates the Serial ATA CRC for the input data stream. The */
-/* generator polynomial used is: */
-/* 32 26 23 22 16 12 11 10 8 7 5 4 2 */
-/* G(x) = x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1 */
-/* */
-/* This sample code uses a parallel implementation of the CRC calculation */
-/* circuit that is suitable for implementation in hardware. A block */
-/* diagram of the circuit being emulated is shown below. */
-/* */
-/* +---+ +---+ +---+ */
-/* Data_In --------->| | | | | R | */
-/* | + |--------->| * |--------->| e |----+ */
-/* +---->| | | | | g | | */
-/* | +---+ +---+ +---+ | */
-/* | | */
-/* | | */
-/* +--------------------------------------------+ */
-/* */
-/* The CRC value is initialized to 0x52325032 as defined in the Serial ATA */
-/* specification. */
-/* */
-/****************************************************************************/
-
-
-
-#include <stdlib.h>
-#include <stdio.h>
-int main(int argc, char *argv[])
-{
- int i;
- unsigned int data_count;
- unsigned int crc;
- unsigned int data_in;
- unsigned char crc_bit[32];
- unsigned char new_bit[32];
-
- crc = 0x52325032;
- data_count = 0;
-
- while((scanf(" 0x%8x", &data_in) == 1) && (!scanf("exit"))) {
- data_count++;
- /* Add the data_in value to the current value of the CRC held in the */
- /* "register". The addition is performed modulo two (XOR). */
- crc ^= data_in;
- /* Expand the value of the CRC held in the register to 32 individual */
- /* bits for easy manipulation. */
- for (i = 0; i < 32; ++i) {
- crc_bit[i] = (crc >> i) & 0x01;
- }
- /* The following 32 assignments perform the function of the box */
- /* labeled "*" in the block diagram above. The new_bit array is a */
- /* temporary holding place for the new CRC value being calculated. */
- /* Note that there are lots of shared terms in the assignments below. */
- new_bit[31] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[25] ^ crc_bit[24] ^
- crc_bit[23] ^ crc_bit[15] ^ crc_bit[11] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[5];
- new_bit[30] = crc_bit[30] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[23] ^
- crc_bit[22] ^ crc_bit[14] ^ crc_bit[10] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[4];
- new_bit[29] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[23] ^
- crc_bit[22] ^ crc_bit[21] ^ crc_bit[13] ^ crc_bit[9] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[3];
- new_bit[28] = crc_bit[30] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[22] ^
- crc_bit[21] ^ crc_bit[20] ^ crc_bit[12] ^ crc_bit[8] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[2];
- new_bit[27] = crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[21] ^
- crc_bit[20] ^ crc_bit[19] ^ crc_bit[11] ^ crc_bit[7] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[1];
- new_bit[26] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[22] ^
- crc_bit[20] ^ crc_bit[19] ^ crc_bit[18] ^ crc_bit[10] ^ crc_bit[6] ^ crc_bit[4] ^ crc_bit[3] ^
- crc_bit[0];
- new_bit[25] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[22] ^ crc_bit[21] ^ crc_bit[19] ^ crc_bit[18] ^
- crc_bit[17] ^ crc_bit[15] ^ crc_bit[11] ^ crc_bit[8] ^ crc_bit[3] ^ crc_bit[2];
- new_bit[24] = crc_bit[30] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[21] ^ crc_bit[20] ^ crc_bit[18] ^ crc_bit[17] ^
- crc_bit[16] ^ crc_bit[14] ^ crc_bit[10] ^ crc_bit[7] ^ crc_bit[2] ^ crc_bit[1];
- new_bit[23] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[20] ^ crc_bit[19] ^ crc_bit[17] ^
- crc_bit[16] ^ crc_bit[15] ^ crc_bit[13] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[1] ^ crc_bit[0];
- new_bit[22] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[19] ^
- crc_bit[18] ^ crc_bit[16] ^ crc_bit[14] ^ crc_bit[12] ^ crc_bit[11] ^ crc_bit[9] ^ crc_bit[0];
- new_bit[21] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[22] ^ crc_bit[18] ^
- crc_bit[17] ^ crc_bit[13] ^ crc_bit[10] ^ crc_bit[9] ^ crc_bit[5];
- new_bit[20] = crc_bit[30] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[23] ^ crc_bit[21] ^ crc_bit[17] ^
- crc_bit[16] ^ crc_bit[12] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[4];
- new_bit[19] = crc_bit[29] ^ crc_bit[27] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[22] ^ crc_bit[20] ^ crc_bit[16] ^
- crc_bit[15] ^ crc_bit[11] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[3];
- new_bit[18] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[21] ^ crc_bit[19] ^
- crc_bit[15] ^ crc_bit[14] ^ crc_bit[10] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[2];
- new_bit[17] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[27] ^ crc_bit[25] ^ crc_bit[23] ^ crc_bit[22] ^ crc_bit[20] ^
- crc_bit[18] ^ crc_bit[14] ^ crc_bit[13] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[1];
- new_bit[16] = crc_bit[30] ^ crc_bit[29] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[22] ^ crc_bit[21] ^ crc_bit[19] ^
- crc_bit[17] ^ crc_bit[13] ^ crc_bit[12] ^ crc_bit[8] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[0];
- new_bit[15] = crc_bit[30] ^ crc_bit[27] ^ crc_bit[24] ^ crc_bit[21] ^ crc_bit[20] ^ crc_bit[18] ^ crc_bit[16] ^
- crc_bit[15] ^ crc_bit[12] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[5] ^ crc_bit[4] ^
- crc_bit[3];
- new_bit[14] = crc_bit[29] ^ crc_bit[26] ^ crc_bit[23] ^ crc_bit[20] ^ crc_bit[19] ^ crc_bit[17] ^ crc_bit[15] ^
- crc_bit[14] ^ crc_bit[11] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[4] ^ crc_bit[3] ^
- crc_bit[2];
- new_bit[13] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[25] ^ crc_bit[22] ^ crc_bit[19] ^ crc_bit[18] ^ crc_bit[16] ^
- crc_bit[14] ^ crc_bit[13] ^ crc_bit[10] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[3] ^
- crc_bit[2] ^ crc_bit[1];
- new_bit[12] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[27] ^ crc_bit[24] ^ crc_bit[21] ^ crc_bit[18] ^ crc_bit[17] ^
- crc_bit[15] ^ crc_bit[13] ^ crc_bit[12] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[4] ^
- crc_bit[2] ^ crc_bit[1] ^ crc_bit[0];
- new_bit[11] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[20] ^
- crc_bit[17] ^ crc_bit[16] ^ crc_bit[15] ^ crc_bit[14] ^ crc_bit[12] ^ crc_bit[9] ^ crc_bit[4] ^
- crc_bit[3] ^ crc_bit[1] ^ crc_bit[0];
- new_bit[10] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[19] ^ crc_bit[16] ^ crc_bit[14] ^
- crc_bit[13] ^ crc_bit[9] ^ crc_bit[5] ^ crc_bit[3] ^ crc_bit[2] ^ crc_bit[0];
- new_bit[9] = crc_bit[29] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[18] ^ crc_bit[13] ^ crc_bit[12] ^ crc_bit[11] ^
- crc_bit[9] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[2] ^ crc_bit[1];
- new_bit[8] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[23] ^ crc_bit[22] ^ crc_bit[17] ^ crc_bit[12] ^ crc_bit[11] ^
- crc_bit[10] ^ crc_bit[8] ^ crc_bit[4] ^ crc_bit[3] ^ crc_bit[1] ^ crc_bit[0];
- new_bit[7] = crc_bit[29] ^ crc_bit[28] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[22] ^ crc_bit[21] ^
- crc_bit[16] ^ crc_bit[15] ^ crc_bit[10] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[5] ^ crc_bit[3] ^
- crc_bit[2] ^ crc_bit[0];
- new_bit[6] = crc_bit[30] ^ crc_bit[29] ^ crc_bit[25] ^ crc_bit[22] ^ crc_bit[21] ^ crc_bit[20] ^ crc_bit[14] ^
- crc_bit[11] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[2] ^
- crc_bit[1];
- new_bit[5] = crc_bit[29] ^ crc_bit[28] ^ crc_bit[24] ^ crc_bit[21] ^ crc_bit[20] ^ crc_bit[19] ^ crc_bit[13] ^
- crc_bit[10] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[3] ^ crc_bit[1] ^
- crc_bit[0];
- new_bit[4] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[29] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[20] ^ crc_bit[19] ^
- crc_bit[18] ^ crc_bit[15] ^ crc_bit[12] ^ crc_bit[11] ^ crc_bit[8] ^ crc_bit[6] ^ crc_bit[4] ^
- crc_bit[3] ^ crc_bit[2] ^ crc_bit[0];
- new_bit[3] = crc_bit[31] ^ crc_bit[27] ^ crc_bit[25] ^ crc_bit[19] ^ crc_bit[18] ^ crc_bit[17] ^ crc_bit[15] ^
- crc_bit[14] ^ crc_bit[10] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[3] ^ crc_bit[2] ^
- crc_bit[1];
- new_bit[2] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[18] ^ crc_bit[17] ^ crc_bit[16] ^
- crc_bit[14] ^ crc_bit[13] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[2] ^
- crc_bit[1] ^ crc_bit[0];
- new_bit[1] = crc_bit[28] ^ crc_bit[27] ^ crc_bit[24] ^ crc_bit[17] ^ crc_bit[16] ^ crc_bit[13] ^ crc_bit[12] ^
- crc_bit[11] ^ crc_bit[9] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[1] ^ crc_bit[0];
- new_bit[0] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^
- crc_bit[16] ^ crc_bit[12] ^ crc_bit[10] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[0];
-
- /* The new CRC value has been calculated as individual bits in the */
- /* new_bit array. Re-assembled it into a 32 bit value and "clock" it */
- /* into the "register". */
- crc = 0;
- for (i = 31; i >= 0; --i) {
- crc = crc << 1;
- crc |= new_bit[i];
- }
- }
- printf("%08x\n", crc);
- return 0;
-}
+++ /dev/null
-import subprocess
-
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.core.link.crc import *
-
-from misoclib.mem.litesata.test.common import *
-
-
-class TB(Module):
- def __init__(self, length, random):
- self.submodules.crc = LiteSATACRC()
- self.length = length
- self.random = random
-
- def get_c_crc(self, datas):
- stdin = ""
- for data in datas:
- stdin += "0x{:08x} ".format(data)
- stdin += "exit"
- with subprocess.Popen("./crc",
- stdin=subprocess.PIPE,
- stdout=subprocess.PIPE) as process:
- process.stdin.write(stdin.encode("ASCII"))
- out, err = process.communicate()
- return int(out.decode("ASCII"), 16)
-
- def gen_simulation(self, selfp):
- # init CRC
- selfp.crc.d = 0
- selfp.crc.ce = 1
- selfp.crc.reset = 1
- yield
- selfp.crc.reset = 0
-
- # feed CRC with datas
- datas = []
- for i in range(self.length):
- data = seed_to_data(i, self.random)
- datas.append(data)
- selfp.crc.d = data
- yield
-
- # log results
- yield
- sim_crc = selfp.crc.value
-
- # stop
- selfp.crc.ce = 0
- for i in range(32):
- yield
-
- # get C core reference
- c_crc = self.get_c_crc(datas)
-
- # check results
- s, l, e = check(c_crc, sim_crc)
- print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
-
-if __name__ == "__main__":
- from migen.sim.generic import run_simulation
- length = 8192
- run_simulation(TB(length, True), ncycles=length+100, vcd_name="my.vcd")
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.core.link import LiteSATALink
-
-from misoclib.mem.litesata.test.model.hdd import *
-from misoclib.mem.litesata.test.common import *
-
-
-class LinkStreamer(PacketStreamer):
- def __init__(self):
- PacketStreamer.__init__(self, link_description(32), LinkTXPacket)
-
-
-class LinkLogger(PacketLogger):
- def __init__(self):
- PacketLogger.__init__(self, link_description(32), LinkRXPacket)
-
-
-class TB(Module):
- def __init__(self):
- self.submodules.hdd = HDD(
- link_debug=False, link_random_level=50,
- transport_debug=False, transport_loopback=True)
- self.submodules.link = InsertReset(LiteSATALink(self.hdd.phy, buffer_depth=512))
-
- self.submodules.streamer = LinkStreamer()
- self.submodules.streamer_randomizer = Randomizer(link_description(32), level=50)
-
- self.submodules.logger_randomizer = Randomizer(link_description(32), level=50)
- self.submodules.logger = LinkLogger()
-
- self.submodules.pipeline = Pipeline(
- self.streamer,
- self.streamer_randomizer,
- self.link,
- self.logger_randomizer,
- self.logger
- )
-
- def gen_simulation(self, selfp):
- for i in range(8):
- streamer_packet = LinkTXPacket([i for i in range(64)])
- yield from self.streamer.send(streamer_packet)
- yield from self.logger.receive()
-
- # check results
- s, l, e = check(streamer_packet, self.logger.packet)
- print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
-
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.core import LiteSATACore
-from misoclib.mem.litesata.frontend.common import *
-from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
-from misoclib.mem.litesata.frontend.bist import LiteSATABISTGenerator, LiteSATABISTChecker
-from misoclib.mem.litesata.frontend.mirroring import LiteSATAMirroring
-
-from misoclib.mem.litesata.test.common import *
-from misoclib.mem.litesata.test.model.hdd import *
-
-
-class TB(Module):
- def __init__(self):
- self.submodules.hdd0 = HDD(n=0,
- link_debug=False, link_random_level=0,
- transport_debug=False, transport_loopback=False,
- hdd_debug=True)
- self.submodules.core0 = LiteSATACore(self.hdd0.phy)
-
- self.submodules.hdd1 = HDD(n=1,
- link_debug=False, link_random_level=0,
- transport_debug=False, transport_loopback=False,
- hdd_debug=True)
- self.submodules.core1 = LiteSATACore(self.hdd1.phy)
-
- self.submodules.mirroring = LiteSATAMirroring([self.core0, self.core1])
-
- self.submodules.crossbar0 = LiteSATACrossbar(self.mirroring.ports[0])
- self.submodules.generator0 = LiteSATABISTGenerator(self.crossbar0.get_port())
- self.submodules.checker0 = LiteSATABISTChecker(self.crossbar0.get_port())
-
- self.submodules.crossbar1 = LiteSATACrossbar(self.mirroring.ports[1])
- self.submodules.generator1 = LiteSATABISTGenerator(self.crossbar1.get_port())
- self.submodules.checker1 = LiteSATABISTChecker(self.crossbar1.get_port())
-
- def gen_simulation(self, selfp):
- hdd0 = self.hdd0
- hdd0.malloc(0, 64)
- hdd1 = self.hdd1
- hdd1.malloc(0, 64)
- sector = 0
- count = 1
- checker0 = selfp.checker0
- checker1 = selfp.checker1
- while True:
- for generator in [selfp.generator0, selfp.generator1]:
- # write data (alternate generators)
- generator.sector = sector
- generator.count = count
- generator.start = 1
- yield
- generator.start = 0
- yield
- while generator.done == 0:
- yield
-
- # verify data on the 2 hdds in //
- checker0.sector = sector
- checker0.count = count
- checker0.start = 1
- checker1.sector = sector
- checker1.count = count
- checker1.start = 1
- yield
- checker0.start = 0
- checker1.start = 0
- yield
- while (checker0.done == 0) or (checker1.done == 0):
- yield
- print("errors {}".format(checker0.errors + checker1.errors))
-
- # prepare next iteration
- sector += 1
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.test.common import *
-
-from misoclib.mem.litesata.test.model.transport import FIS_REG_H2D, FIS_DATA
-
-
-class CommandLayer(Module):
- def __init__(self, transport):
- self.transport = transport
- self.transport.set_command(self)
-
- self.hdd = None
- self.n = None
-
- def set_hdd(self, hdd):
- self.hdd = hdd
- self.transport.n = hdd.n
- self.transport.link.n = hdd.n
-
- def callback(self, fis):
- resp = None
- if isinstance(fis, FIS_REG_H2D):
- if fis.command == regs["WRITE_DMA_EXT"]:
- resp = self.hdd.write_dma_callback(fis)
- elif fis.command == regs["READ_DMA_EXT"]:
- resp = self.hdd.read_dma_callback(fis)
- elif isinstance(fis, FIS_DATA):
- resp = self.hdd.data_callback(fis)
-
- if resp is not None:
- for packet in resp:
- self.transport.send(packet)
+++ /dev/null
-import math
-
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.test.common import *
-
-from misoclib.mem.litesata.test.model.phy import *
-from misoclib.mem.litesata.test.model.link import *
-from misoclib.mem.litesata.test.model.transport import *
-from misoclib.mem.litesata.test.model.command import *
-
-
-def print_hdd(s, n=None):
- print_with_prefix(s, "[HDD{}]: ".format("" if n is None else str(n)))
-
-
-class HDDMemRegion:
- def __init__(self, base, count, sector_size):
- self.base = base
- self.count = count
- self.data = [0]*(count*sector_size//4)
-
-
-class HDD(Module):
- def __init__(self, n=None,
- link_debug=False, link_random_level=0,
- transport_debug=False, transport_loopback=False,
- hdd_debug=False,
- ):
- self.n = n
- self.submodules.phy = PHYLayer()
- self.submodules.link = LinkLayer(self.phy, link_debug, link_random_level)
- self.submodules.transport = TransportLayer(self.link, transport_debug, transport_loopback)
- self.submodules.command = CommandLayer(self.transport)
-
- self.command.set_hdd(self)
-
- self.debug = hdd_debug
- self.mem = None
- self.wr_sector = 0
- self.wr_end_sector = 0
- self.rd_sector = 0
- self.rx_end_sector = 0
-
- def malloc(self, sector, count):
- if self.debug:
- s = "Allocating {n} sectors: {s} to {e}".format(n=count, s=sector, e=sector+count-1)
- s += " ({} KB)".format(count*logical_sector_size//1024)
- print_hdd(s, self.n)
- self.mem = HDDMemRegion(sector, count, logical_sector_size)
-
- def write(self, sector, data):
- n = math.ceil(dwords2sectors(len(data)))
- if self.debug:
- if n == 1:
- s = "{}".format(sector)
- else:
- s = "{s} to {e}".format(s=sector, e=sector+n-1)
- print_hdd("Writing sector " + s, self.n)
- for i in range(len(data)):
- offset = sectors2dwords(sector)
- self.mem.data[offset+i] = data[i]
-
- def read(self, sector, count):
- if self.debug:
- if count == 1:
- s = "{}".format(sector)
- else:
- s = "{s} to {e}".format(s=sector, e=sector+count-1)
- print_hdd("Reading sector " + s, self.n)
- data = []
- for i in range(sectors2dwords(count)):
- data.append(self.mem.data[sectors2dwords(sector)+i])
- return data
-
- def write_dma_callback(self, fis):
- self.wr_sector = fis.lba_lsb + (fis.lba_msb << 32)
- self.wr_end_sector = self.wr_sector + fis.count
- return [FIS_DMA_ACTIVATE_D2H()]
-
- def read_dma_callback(self, fis):
- self.rd_sector = fis.lba_lsb + (fis.lba_msb << 32)
- self.rd_end_sector = self.rd_sector + fis.count
- packets = []
- while self.rd_sector != self.rd_end_sector:
- count = min(self.rd_end_sector-self.rd_sector, (fis_max_dwords*4)//logical_sector_size)
- packet = self.read(self.rd_sector, count)
- packet.insert(0, 0)
- packets.append(FIS_DATA(packet, direction="D2H"))
- self.rd_sector += count
- packets.append(FIS_REG_D2H())
- return packets
-
- def data_callback(self, fis):
- self.write(self.wr_sector, fis.packet[1:])
- self.wr_sector += dwords2sectors(len(fis.packet[1:]))
- if self.wr_sector == self.wr_end_sector:
- return [FIS_REG_D2H()]
- else:
- return [FIS_DMA_ACTIVATE_D2H()]
+++ /dev/null
-import subprocess
-import math
-
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.test.common import *
-
-
-def print_link(s, n=None):
- print_with_prefix(s, "[LNK{}]: ".format("" if n is None else str(n)))
-
-
-def import_scrambler_datas():
- with subprocess.Popen(["./scrambler"],
- stdin=subprocess.PIPE,
- stdout=subprocess.PIPE) as process:
- process.stdin.write("0x10000".encode("ASCII"))
- out, err = process.communicate()
- return [int(e, 16) for e in out.decode("utf-8").split("\n")[:-1]]
-
-
-class LinkPacket(list):
- def __init__(self, init=[]):
- self.ongoing = False
- self.done = False
- self.scrambled_datas = import_scrambler_datas()
- for dword in init:
- self.append(dword)
-
-
-class LinkRXPacket(LinkPacket):
- def descramble(self):
- for i in range(len(self)):
- self[i] = self[i] ^ self.scrambled_datas[i]
-
- def check_crc(self):
- stdin = ""
- for v in self[:-1]:
- stdin += "0x{:08x} ".format(v)
- stdin += "exit"
- with subprocess.Popen("./crc",
- stdin=subprocess.PIPE,
- stdout=subprocess.PIPE) as process:
- process.stdin.write(stdin.encode("ASCII"))
- out, err = process.communicate()
- crc = int(out.decode("ASCII"), 16)
- r = (self[-1] == crc)
- self.pop()
- return r
-
- def decode(self):
- self.descramble()
- return self.check_crc()
-
-
-class LinkTXPacket(LinkPacket):
- def insert_crc(self):
- stdin = ""
- for v in self:
- stdin += "0x{:08x} ".format(v)
- stdin += "exit"
- with subprocess.Popen("./crc",
- stdin=subprocess.PIPE,
- stdout=subprocess.PIPE) as process:
- process.stdin.write(stdin.encode("ASCII"))
- out, err = process.communicate()
- crc = int(out.decode("ASCII"), 16)
- self.append(crc)
-
- def scramble(self):
- for i in range(len(self)):
- self[i] = self[i] ^ self.scrambled_datas[i]
-
- def encode(self):
- self.insert_crc()
- self.scramble()
-
-
-class LinkLayer(Module):
- def __init__(self, phy, debug=False, random_level=0):
- self.phy = phy
- self.debug = debug
- self.random_level = random_level
- self.tx_packets = []
- self.tx_packet = LinkTXPacket()
- self.rx_packet = LinkRXPacket()
-
- self.rx_cont = False
- self.rx_last = 0
- self.tx_cont = False
- self.tx_cont_nb = -1
- self.tx_lasts = [0, 0, 0]
-
- self.scrambled_datas = import_scrambler_datas()
-
- self.transport = None
- self.n = None
-
- self.send_state = ""
- self.send_states = ["RDY", "SOF", "DATA", "EOF", "WTRM"]
-
- def set_transport(self, transport):
- self.transport = transport
-
- def send(self, dword):
- if self.send_state == "RDY":
- self.phy.send(primitives["X_RDY"])
- if dword == primitives["R_RDY"]:
- self.send_state = "SOF"
- elif self.send_state == "SOF":
- self.phy.send(primitives["SOF"])
- self.send_state = "DATA"
- elif self.send_state == "DATA":
- if dword == primitives["HOLD"]:
- self.phy.send(primitives["HOLDA"])
- else:
- self.phy.send(self.tx_packet.pop(0))
- if len(self.tx_packet) == 0:
- self.send_state = "EOF"
- elif self.send_state == "EOF":
- self.phy.send(primitives["EOF"])
- self.send_state = "WTRM"
- elif self.send_state == "WTRM":
- self.phy.send(primitives["WTRM"])
- if dword == primitives["R_OK"]:
- self.tx_packet.done = True
- elif dword == primitives["R_ERR"]:
- self.tx_packet.done = True
- if self.tx_packet.done:
- self.phy.send(primitives["SYNC"])
-
- def insert_cont(self):
- self.tx_lasts.pop(0)
- self.tx_lasts.append(self.phy.tx.dword.dat)
- self.tx_cont = True
- for i in range(3):
- if not is_primitive(self.tx_lasts[i]):
- self.tx_cont = False
- if self.tx_lasts[i] != self.tx_lasts[0]:
- self.tx_cont = False
- if self.tx_cont:
- if self.tx_cont_nb == 0:
- self.phy.send(primitives["CONT"])
- else:
- self.phy.send(self.scrambled_datas[self.tx_cont_nb])
- self.tx_cont_nb += 1
- else:
- self.tx_cont_nb = 0
-
- def remove_cont(self, dword):
- if dword == primitives["HOLD"]:
- if self.rx_cont:
- self.tx_lasts = [0, 0, 0]
- if dword == primitives["CONT"]:
- self.rx_cont = True
- elif is_primitive(dword):
- self.rx_last = dword
- self.rx_cont = False
- if self.rx_cont:
- dword = self.rx_last
- return dword
-
- def callback(self, dword):
- if dword == primitives["X_RDY"]:
- self.phy.send(primitives["R_RDY"])
- elif dword == primitives["WTRM"]:
- self.phy.send(primitives["R_OK"])
- if self.rx_packet.ongoing:
- self.rx_packet.decode()
- if self.transport is not None:
- self.transport.callback(self.rx_packet)
- self.rx_packet.ongoing = False
- elif dword == primitives["HOLD"]:
- self.phy.send(primitives["HOLDA"])
- elif dword == primitives["EOF"]:
- pass
- elif self.rx_packet.ongoing:
- if dword != primitives["HOLD"]:
- n = randn(100)
- if n < self.random_level:
- self.phy.send(primitives["HOLD"])
- else:
- self.phy.send(primitives["R_IP"])
- if not is_primitive(dword):
- self.rx_packet.append(dword)
- elif dword == primitives["SOF"]:
- self.rx_packet = LinkRXPacket()
- self.rx_packet.ongoing = True
-
- def gen_simulation(self, selfp):
- self.tx_packet.done = True
- self.phy.send(primitives["SYNC"])
- while True:
- yield from self.phy.receive()
- if self.debug:
- print_link(self.phy, self.n)
- self.phy.send(primitives["SYNC"])
- rx_dword = self.phy.rx.dword.dat
- rx_dword = self.remove_cont(rx_dword)
- if len(self.tx_packets) != 0:
- if self.tx_packet.done:
- self.tx_packet = self.tx_packets.pop(0)
- self.tx_packet.encode()
- self.send_state = "RDY"
- if not self.tx_packet.done:
- self.send(rx_dword)
- else:
- self.callback(rx_dword)
- self.insert_cont()
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.test.common import *
-
-class PHYDword:
- def __init__(self, dat=0):
- self.dat = dat
- self.start = 1
- self.done = 0
-
-
-class PHYSource(Module):
- def __init__(self):
- self.source = Source(phy_description(32))
-
- # # #
-
- self.dword = PHYDword()
-
- def send(self, dword):
- self.dword = dword
-
- def do_simulation(self, selfp):
- selfp.source.stb = 1
- selfp.source.charisk = 0b0000
- for k, v in primitives.items():
- if v == self.dword.dat:
- selfp.source.charisk = 0b0001
- selfp.source.data = self.dword.dat
-
-
-class PHYSink(Module):
- def __init__(self):
- self.sink = Sink(phy_description(32))
-
- # # #
-
- self.dword = PHYDword()
-
- def receive(self):
- self.dword.done = 0
- while self.dword.done == 0:
- yield
-
- def do_simulation(self, selfp):
- self.dword.done = 0
- selfp.sink.ack = 1
- if selfp.sink.stb == 1:
- self.dword.done = 1
- self.dword.dat = selfp.sink.data
-
-
-class PHYLayer(Module):
- def __init__(self):
-
- self.submodules.rx = PHYSink()
- self.submodules.tx = PHYSource()
-
- self.source = self.tx.source
- self.sink = self.rx.sink
-
- def send(self, dword):
- packet = PHYDword(dword)
- self.tx.send(packet)
-
- def receive(self):
- yield from self.rx.receive()
-
- def __repr__(self):
- receiving = "{:08x} ".format(self.rx.dword.dat)
- receiving += decode_primitive(self.rx.dword.dat)
- receiving += " "*(16-len(receiving))
-
- sending = "{:08x} ".format(self.tx.dword.dat)
- sending += decode_primitive(self.tx.dword.dat)
- sending += " "*(16-len(sending))
-
- return receiving + sending
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.test.common import *
-
-from misoclib.mem.litesata.test.model.link import LinkTXPacket
-
-
-def print_transport(s, n=None):
- print_with_prefix(s, "[TRN{}]: ".format("" if n is None else str(n)))
-
-
-def get_field_data(field, packet):
- return (packet[field.byte//4] >> field.offset) & (2**field.width-1)
-
-
-class FIS:
- def __init__(self, packet, description, direction="H2D"):
- self.packet = packet
- self.description = description
- self.direction = direction
- self.decode()
-
- def decode(self):
- for k, v in self.description.items():
- setattr(self, k, get_field_data(v, self.packet))
-
- def encode(self):
- for k, v in self.description.items():
- self.packet[v.byte//4] |= (getattr(self, k) << v.offset)
-
- def __repr__(self):
- if self.direction == "H2D":
- r = ">>>>>>>>\n"
- else:
- r = "<<<<<<<<\n"
- for k in sorted(self.description.keys()):
- r += k + " : 0x{:x}".format(getattr(self, k)) + "\n"
- return r
-
-
-class FIS_REG_H2D(FIS):
- def __init__(self, packet=[0]*fis_reg_h2d_header.length):
- FIS.__init__(self, packet, fis_reg_h2d_header.fields)
- self.type = fis_types["REG_H2D"]
- self.direction = "H2D"
-
- def __repr__(self):
- r = "FIS_REG_H2D\n"
- r += FIS.__repr__(self)
- return r
-
-
-class FIS_REG_D2H(FIS):
- def __init__(self, packet=[0]*fis_reg_d2h_header.length):
- FIS.__init__(self, packet, fis_reg_d2h_header.fields)
- self.type = fis_types["REG_D2H"]
- self.direction = "D2H"
-
- def __repr__(self):
- r = "FIS_REG_D2H\n"
- r += FIS.__repr__(self)
- return r
-
-
-class FIS_DMA_ACTIVATE_D2H(FIS):
- def __init__(self, packet=[0]*fis_dma_activate_d2h_header.length):
- FIS.__init__(self, packet, fis_dma_activate_d2h_header.fields)
- self.type = fis_types["DMA_ACTIVATE_D2H"]
- self.direction = "D2H"
-
- def __repr__(self):
- r = "FIS_DMA_ACTIVATE_D2H\n"
- r += FIS.__repr__(self)
- return r
-
-
-class FIS_DATA(FIS):
- def __init__(self, packet=[0], direction="H2D"):
- FIS.__init__(self, packet, fis_data_header.fields, direction)
- self.type = fis_types["DATA"]
-
- def __repr__(self):
- r = "FIS_DATA\n"
- r += FIS.__repr__(self)
- for data in self.packet[1:]:
- r += "{:08x}\n".format(data)
- return r
-
-
-class FIS_UNKNOWN(FIS):
- def __init__(self, packet=[0], direction="H2D"):
- FIS.__init__(self, packet, {}, direction)
-
- def __repr__(self):
- r = "UNKNOWN\n"
- if self.direction == "H2D":
- r += ">>>>>>>>\n"
- else:
- r += "<<<<<<<<\n"
- for dword in self.packet:
- r += "{:08x}\n".format(dword)
- return r
-
-
-class TransportLayer(Module):
- def __init__(self, link, debug=False, loopback=False):
- self.link = link
- self.debug = debug
- self.loopback = loopback
- self.link.set_transport(self)
-
- self.command = None
- self.n = None
-
- def set_command(self, command):
- self.command = command
-
- def send(self, fis):
- fis.encode()
- packet = LinkTXPacket(fis.packet)
- self.link.tx_packets.append(packet)
- if self.debug and not self.loopback:
- print_transport(fis, self.n)
-
- def callback(self, packet):
- fis_type = packet[0] & 0xff
- if fis_type == fis_types["REG_H2D"]:
- fis = FIS_REG_H2D(packet)
- elif fis_type == fis_types["REG_D2H"]:
- fis = FIS_REG_D2H(packet)
- elif fis_type == fis_types["DMA_ACTIVATE_D2H"]:
- fis = FIS_DMA_ACTIVATE_D2H(packet)
- elif fis_type == fis_types["DATA"]:
- fis = FIS_DATA(packet, direction="H2D")
- else:
- fis = FIS_UNKNOWN(packet, direction="H2D")
- if self.debug:
- print_transport(fis, self.n)
- if self.loopback:
- self.send(fis)
- else:
- self.command.callback(fis)
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.phy.datapath import LiteSATAPHYDatapath
-
-from misoclib.mem.litesata.test.common import *
-
-
-class DataPacket(list):
- def __init__(self, data=[]):
- self.ongoing = False
- self.done = False
- for d in data:
- self.append(d)
-
-
-class DataStreamer(PacketStreamer):
- def __init__(self):
- PacketStreamer.__init__(self, phy_description(32), DataPacket)
-
- def do_simulation(self, selfp):
- PacketStreamer.do_simulation(self, selfp)
- selfp.source.charisk = 0
- # Note: for simplicity we generate charisk by detecting
- # primitives in data
- for k, v in primitives.items():
- try:
- if self.source_data == v:
- selfp.source.charisk = 0b0001
- except:
- pass
-
-
-class DataLogger(PacketLogger):
- def __init__(self):
- PacketLogger.__init__(self, phy_description(32), DataPacket)
-
-
-class TRX(Module):
- def __init__(self):
- self.sink = Sink(phy_description(32))
- self.source = Source(phy_description(32))
- self.comb += Record.connect(self.sink, self.source)
-
-
-class CTRL(Module):
- def __init__(self):
- self.sink = Sink(phy_description(32))
- self.source = Source(phy_description(32))
- self.ready = Signal(reset=1)
-
-
-class TB(Module):
- def __init__(self):
- # use sys_clk for each clock_domain
- self.clock_domains.cd_sata_rx = ClockDomain()
- self.clock_domains.cd_sata_tx = ClockDomain()
- self.comb += [
- self.cd_sata_rx.clk.eq(ClockSignal()),
- self.cd_sata_rx.rst.eq(ResetSignal()),
- self.cd_sata_tx.clk.eq(ClockSignal()),
- self.cd_sata_tx.rst.eq(ResetSignal()),
- ]
-
- self.submodules.streamer = DataStreamer()
- self.submodules.streamer_randomizer = Randomizer(phy_description(32), level=10)
- self.submodules.trx = TRX()
- self.submodules.ctrl = CTRL()
- self.submodules.datapath = LiteSATAPHYDatapath(self.trx, self.ctrl)
- self.submodules.logger_randomizer = Randomizer(phy_description(32), level=10)
- self.submodules.logger = DataLogger()
-
- self.submodules.pipeline = Pipeline(
- self.streamer,
- self.streamer_randomizer,
- self.datapath,
- self.logger_randomizer,
- self.logger
- )
-
- def gen_simulation(self, selfp):
- streamer_packet = DataPacket([seed_to_data(i, False) for i in range(512)])
- yield from self.streamer.send(streamer_packet)
- yield from self.logger.receive(512)
- for d in self.logger.packet:
- r = "{:08x} ".format(d)
- r += decode_primitive(d)
- print(r)
-
- # check results
- #s, l, e = check(streamer_packet, self.logger.packet)
- #print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
-
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)
+++ /dev/null
-// Adapted from SATA specification
-/****************************************************************************/
-/* */
-/* scramble.c */
-/* */
-/* This sample code generates the entire sequence of 65535 Dwords produced */
-/* by the scrambler defined in the Serial ATA specification. The */
-/* specification calls for an LFSR to generate a string of bits that will */
-/* be packaged into 32 bit Dwords to be XORed with the data Dwords. The */
-/* generator polynomial specified is: */
-/* 16 15 13 4 */
-/* G(x) = x + x + x + x + 1 */
-/* */
-/* Parallelized versions of the scrambler are initialized to a value */
-/* derived from the initialization value of 0xFFFF defined in the */
-/* specification. This implementation is initialized to 0xF0F6. Other */
-/* parallel implementations will have different initial values. The */
-/* important point is that the first Dword output of any implementation */
-/* must equal 0xC2D2768D. */
-/* This code does not represent an elegant solution for a C implementation, */
-/* but it does demonstrate a method of generating the sequence that can be */
-/* easily implemented in hardware. A block diagram of the circuit emulated */
-/* by this code is shown below. */
-/* */
-/* +-----------------------------------+ */
-/* | | */
-/* | | */
-/* | +---+ +---+ | */
-/* | | R | | * | | */
-/* +---->| e |----------+---->| M |----+----> Output(31 downto 16) */
-/* | g | | | 1 | */
-/* +---+ | +---+ */
-/* | */
-/* | +---+ */
-/* | | * | */
-/* +---->| M |---------> Output(15 downto 0) */
-/* | 2 | */
-/* +---+ */
-/* */
-/* The register shown in the block diagram is a 16 bit register. The two */
-/* boxes, *M1 and *M2, each represent a multiply by a 16 by 16 binary */
-/* matrix. A 16 by 16 matrix times a 16 bit vector yields a 16 bit vector. */
-/* The two vectors are the two halves of the 32 bit scrambler value. The */
-/* upper half of the scrambler value is stored back into the context */
-/* register to be used to generate the next value in the scrambler */
-/* */
-/****************************************************************************/
-#include <stdlib.h>
-#include <stdio.h>
-int main(int argc, char *argv[])
-{
- int i, j;
- unsigned int length;
- unsigned short context;
- unsigned long scrambler;
- unsigned char now[16];
- unsigned char next[32];
- context = 0xF0F6;
-
- scanf("0x%8x", &length);
-
- for (i = 0; i < length; ++i) {
- for (j = 0; j < 16; ++j) {
- now[j] = (context >> j) & 0x01;
- }
- next[31] = now[12] ^ now[10] ^ now[7] ^ now[3] ^ now[1] ^ now[0];
- next[30] = now[15] ^ now[14] ^ now[12] ^ now[11] ^ now[9] ^ now[6] ^ now[3] ^ now[2] ^ now[0];
- next[29] = now[15] ^ now[13] ^ now[12] ^ now[11] ^ now[10] ^ now[8] ^ now[5] ^ now[3] ^ now[2] ^ now[1];
- next[28] = now[14] ^ now[12] ^ now[11] ^ now[10] ^ now[9] ^ now[7] ^ now[4] ^ now[2] ^ now[1] ^ now[0];
- next[27] = now[15] ^ now[14] ^ now[13] ^ now[12] ^ now[11] ^ now[10] ^ now[9] ^ now[8] ^ now[6] ^ now[1] ^ now[0];
- next[26] = now[15] ^ now[13] ^ now[11] ^ now[10] ^ now[9] ^ now[8] ^ now[7] ^ now[5] ^ now[3] ^ now[0];
- next[25] = now[15] ^ now[10] ^ now[9] ^ now[8] ^ now[7] ^ now[6] ^ now[4] ^ now[3] ^ now[2];
- next[24] = now[14] ^ now[9] ^ now[8] ^ now[7] ^ now[6] ^ now[5] ^ now[3] ^ now[2] ^ now[1];
- next[23] = now[13] ^ now[8] ^ now[7] ^ now[6] ^ now[5] ^ now[4] ^ now[2] ^ now[1] ^ now[0];
- next[22] = now[15] ^ now[14] ^ now[7] ^ now[6] ^ now[5] ^ now[4] ^ now[1] ^ now[0];
- next[21] = now[15] ^ now[13] ^ now[12] ^ now[6] ^ now[5] ^ now[4] ^ now[0];
- next[20] = now[15] ^ now[11] ^ now[5] ^ now[4];
- next[19] = now[14] ^ now[10] ^ now[4] ^ now[3];
- next[18] = now[13] ^ now[9] ^ now[3] ^ now[2];
- next[17] = now[12] ^ now[8] ^ now[2] ^ now[1];
- next[16] = now[11] ^ now[7] ^ now[1] ^ now[0];
-
-
- next[15] = now[15] ^ now[14] ^ now[12] ^ now[10] ^ now[6] ^ now[3] ^ now[0];
- next[14] = now[15] ^ now[13] ^ now[12] ^ now[11] ^ now[9] ^ now[5] ^ now[3] ^ now[2];
- next[13] = now[14] ^ now[12] ^ now[11] ^ now[10] ^ now[8] ^ now[4] ^ now[2] ^ now[1];
- next[12] = now[13] ^ now[11] ^ now[10] ^ now[9] ^ now[7] ^ now[3] ^ now[1] ^ now[0];
- next[11] = now[15] ^ now[14] ^ now[10] ^ now[9] ^ now[8] ^ now[6] ^ now[3] ^ now[2] ^ now[0];
- next[10] = now[15] ^ now[13] ^ now[12] ^ now[9] ^ now[8] ^ now[7] ^ now[5] ^ now[3] ^ now[2] ^ now[1];
- next[9] = now[14] ^ now[12] ^ now[11] ^ now[8] ^ now[7] ^ now[6] ^ now[4] ^ now[2] ^ now[1] ^ now[0];
- next[8] = now[15] ^ now[14] ^ now[13] ^ now[12] ^ now[11] ^ now[10] ^ now[7] ^ now[6] ^ now[5] ^ now[1] ^ now[0];
- next[7] = now[15] ^ now[13] ^ now[11] ^ now[10] ^ now[9] ^ now[6] ^ now[5] ^ now[4] ^ now[3] ^ now[0];
- next[6] = now[15] ^ now[10] ^ now[9] ^ now[8] ^ now[5] ^ now[4] ^ now[2];
- next[5] = now[14] ^ now[9] ^ now[8] ^ now[7] ^ now[4] ^ now[3] ^ now[1];
- next[4] = now[13] ^ now[8] ^ now[7] ^ now[6] ^ now[3] ^ now[2] ^ now[0];
- next[3] = now[15] ^ now[14] ^ now[7] ^ now[6] ^ now[5] ^ now[3] ^ now[2] ^ now[1];
- next[2] = now[14] ^ now[13] ^ now[6] ^ now[5] ^ now[4] ^ now[2] ^ now[1] ^ now[0];
- next[1] = now[15] ^ now[14] ^ now[13] ^ now[5] ^ now[4] ^ now[1] ^ now[0];
- next[0] = now[15] ^ now[13] ^ now[4] ^ now[0];
-
- scrambler = 0;
- for (j = 31; j >= 0; --j) {
- scrambler = scrambler << 1;
- scrambler |= next[j];
- }
- context = scrambler >> 16;
- printf("%08x\n", (unsigned int) scrambler);
-
- }
-
- return 0;
-
-}
\ No newline at end of file
+++ /dev/null
-import subprocess
-
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.core.link.scrambler import *
-
-from misoclib.mem.litesata.test.common import *
-
-
-class TB(Module):
- def __init__(self, length):
- self.submodules.scrambler = InsertReset(Scrambler())
- self.length = length
-
- def get_c_values(self, length):
- stdin = "0x{:08x}".format(length)
- with subprocess.Popen("./scrambler",
- stdin=subprocess.PIPE,
- stdout=subprocess.PIPE) as process:
- process.stdin.write(stdin.encode("ASCII"))
- out, err = process.communicate()
- return [int(e, 16) for e in out.decode("ASCII").split("\n")[:-1]]
-
- def gen_simulation(self, selfp):
- # init CRC
- selfp.scrambler.ce = 1
- selfp.scrambler.reset = 1
- yield
- selfp.scrambler.reset = 0
-
- # log results
- yield
- sim_values = []
- for i in range(self.length):
- sim_values.append(selfp.scrambler.value)
- yield
-
- # stop
- selfp.scrambler.ce = 0
- for i in range(32):
- yield
-
- # get C code reference
- c_values = self.get_c_values(self.length)
-
- # check results
- s, l, e = check(c_values, sim_values)
- print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
-
-if __name__ == "__main__":
- from migen.sim.generic import run_simulation
- length = 8192
- run_simulation(TB(length), ncycles=length+100, vcd_name="my.vcd")
+++ /dev/null
-from misoclib.mem.litesata.common import *
-from misoclib.mem.litesata.core import LiteSATACore
-from misoclib.mem.litesata.frontend.common import *
-from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
-from misoclib.mem.litesata.frontend.bist import LiteSATABISTGenerator, LiteSATABISTChecker
-from misoclib.mem.litesata.frontend.striping import LiteSATAStriping
-
-from misoclib.mem.litesata.test.common import *
-from misoclib.mem.litesata.test.model.hdd import *
-
-
-class TB(Module):
- def __init__(self):
- self.submodules.hdd0 = HDD(n=0,
- link_debug=False, link_random_level=0,
- transport_debug=False, transport_loopback=False,
- hdd_debug=True)
- self.submodules.core0 = LiteSATACore(self.hdd0.phy)
-
- self.submodules.hdd1 = HDD(n=1,
- link_debug=False, link_random_level=0,
- transport_debug=False, transport_loopback=False,
- hdd_debug=True)
- self.submodules.core1 = LiteSATACore(self.hdd1.phy)
-
- self.submodules.striping = LiteSATAStriping([self.core0, self.core1])
- self.submodules.crossbar = LiteSATACrossbar(self.striping)
-
- self.submodules.generator = LiteSATABISTGenerator(self.crossbar.get_port())
- self.submodules.checker = LiteSATABISTChecker(self.crossbar.get_port())
-
- def gen_simulation(self, selfp):
- hdd0 = self.hdd0
- hdd0.malloc(0, 64)
- hdd1 = self.hdd1
- hdd1.malloc(0, 64)
- sector = 0
- count = 1
- generator = selfp.generator
- checker = selfp.checker
- while True:
- # write data
- generator.sector = sector
- generator.count = count
- generator.start = 1
- yield
- generator.start = 0
- yield
- while generator.done == 0:
- yield
-
- # verify data
- checker.sector = sector
- checker.count = count
- checker.start = 1
- yield
- checker.start = 0
- yield
- while checker.done == 0:
- yield
- print("errors {}".format(checker.errors))
-
- # prepare next iteration
- sector += 1
- count = max((count + 1)%8, 1)
-
-if __name__ == "__main__":
- run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)
projects / litex.git / commitdiff
