Do not modify design modules while iterating over `modules()`.

Co-Authored-By: Eddie Hung <eddie@fpgeh.com>

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index f300c2f7217509c3c346bbcae31d66fcdb546e59..930b4c41635450d109e7e0730774523d379eebbd 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -1423,11 +1423,14 @@ struct FlattenPass : public Pass {
                                                        new_used_modules.insert(cell->type);
                        }
 
+                       std::set<RTLIL::Module *> to_remove;
                        for (auto mod : design->modules())
                                if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) {
                                        log("Deleting now unused module %s.\n", log_id(mod));
-                                       design->remove(mod);
+                                       to_remove.insert(mod);
                                }
+                       for (auto mod : to_remove)
+                               design->remove(mod);
                }
 
                log_pop();