xilinx_ise: enable register balancing

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 63e68bfc426bdda5eb0247d566edb496029f8a8c..85d277122a54fbdbf81950ed0abeb05d1f01c59a 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -81,6 +81,7 @@ def _build_files(device, sources, named_sc, named_pc, build_name):
 -ifmt MIXED
 -opt_mode SPEED
 -reduce_control_sets auto
+-register_balancing yes
 -ofn %s.ngc
 -p %s""" % (build_name, build_name, device)
        tools.write_to_file(build_name + ".xst", xst_contents)