[30/77] Use scalar_int_mode for doubleword splits

This patch uses is_a <scalar_int_mode> in a couple of places that
were splitting doubleword integer operations into word_mode
operations.  It also uses scalar_int_mode in the expand_expr_real_2
handling of doubleword shifts.

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* expr.c (expand_expr_real_2): Use scalar_int_mode for the
	double-word mode.
	* lower-subreg.c (resolve_shift_zext): Use is_a <scalar_int_mode>.
	* optabs.c (expand_unop): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r251482

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9337cdaa7d9c90a9f0946c1770050e80fdbfd784..5beaf455fe7bef662c5dd44e03fd1366ee2de67e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
+           Alan Hayward  <alan.hayward@arm.com>
+           David Sherwood  <david.sherwood@arm.com>
+
+       * expr.c (expand_expr_real_2): Use scalar_int_mode for the
+       double-word mode.
+       * lower-subreg.c (resolve_shift_zext): Use is_a <scalar_int_mode>.
+       * optabs.c (expand_unop): Likewise.
+
 2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
            Alan Hayward  <alan.hayward@arm.com>
            David Sherwood  <david.sherwood@arm.com>

diff --git a/gcc/expr.c b/gcc/expr.c
index ce5f42e0ea6f4770f3cfdc864046e2d4a6d3b907..ea1a6d4a9cd00c94f01d1716f222266d48c6416f 100644 (file)
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -8208,6 +8208,7 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
   tree type;
   int unsignedp;
   machine_mode mode;
+  scalar_int_mode int_mode;
   enum tree_code code = ops->code;
   optab this_optab;
   rtx subtarget, original_target;
@@ -9171,8 +9172,8 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
        if (code == LSHIFT_EXPR
            && target
            && REG_P (target)
-           && mode == GET_MODE_WIDER_MODE (word_mode).else_void ()
-           && GET_MODE_SIZE (mode) == 2 * GET_MODE_SIZE (word_mode)
+           && GET_MODE_2XWIDER_MODE (word_mode).exists (&int_mode)
+           && mode == int_mode
            && TREE_CONSTANT (treeop1)
            && TREE_CODE (treeop0) == SSA_NAME)
          {
@@ -9183,20 +9184,20 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
                machine_mode rmode = TYPE_MODE
                  (TREE_TYPE (gimple_assign_rhs1 (def)));
 
-               if (GET_MODE_SIZE (rmode) < GET_MODE_SIZE (mode)
+               if (GET_MODE_SIZE (rmode) < GET_MODE_SIZE (int_mode)
                    && TREE_INT_CST_LOW (treeop1) < GET_MODE_BITSIZE (word_mode)
                    && ((TREE_INT_CST_LOW (treeop1) + GET_MODE_BITSIZE (rmode))
                        >= GET_MODE_BITSIZE (word_mode)))
                  {
                    rtx_insn *seq, *seq_old;
                    unsigned int high_off = subreg_highpart_offset (word_mode,
-                                                                   mode);
+                                                                   int_mode);
                    bool extend_unsigned
                      = TYPE_UNSIGNED (TREE_TYPE (gimple_assign_rhs1 (def)));
-                   rtx low = lowpart_subreg (word_mode, op0, mode);
-                   rtx dest_low = lowpart_subreg (word_mode, target, mode);
+                   rtx low = lowpart_subreg (word_mode, op0, int_mode);
+                   rtx dest_low = lowpart_subreg (word_mode, target, int_mode);
                    rtx dest_high = simplify_gen_subreg (word_mode, target,
-                                                        mode, high_off);
+                                                        int_mode, high_off);
                    HOST_WIDE_INT ramount = (BITS_PER_WORD
                                             - TREE_INT_CST_LOW (treeop1));
                    tree rshift = build_int_cst (TREE_TYPE (treeop1), ramount);
@@ -9219,12 +9220,13 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
                    end_sequence ();
                    temp = target ;
 
-                   if (have_insn_for (ASHIFT, mode))
+                   if (have_insn_for (ASHIFT, int_mode))
                      {
                        bool speed_p = optimize_insn_for_speed_p ();
                        start_sequence ();
-                       rtx ret_old = expand_variable_shift (code, mode, op0,
-                                                            treeop1, target,
+                       rtx ret_old = expand_variable_shift (code, int_mode,
+                                                            op0, treeop1,
+                                                            target,
                                                             unsignedp);
 
                        seq_old = get_insns ();

diff --git a/gcc/lower-subreg.c b/gcc/lower-subreg.c
index bdec0aa4cc0ce024ce9cc0c6f41728595ff4719b..99ad2532b644959b77d7b0d13104238f76d8ba6a 100644 (file)
--- a/gcc/lower-subreg.c
+++ b/gcc/lower-subreg.c
@@ -1214,6 +1214,7 @@ resolve_shift_zext (rtx_insn *insn)
   rtx_insn *insns;
   rtx src_reg, dest_reg, dest_upper, upper_src = NULL_RTX;
   int src_reg_num, dest_reg_num, offset1, offset2, src_offset;
+  scalar_int_mode inner_mode;
 
   set = single_set (insn);
   if (!set)
@@ -1227,6 +1228,8 @@ resolve_shift_zext (rtx_insn *insn)
     return NULL;
 
   op_operand = XEXP (op, 0);
+  if (!is_a <scalar_int_mode> (GET_MODE (op_operand), &inner_mode))
+    return NULL;
 
   /* We can tear this operation apart only if the regs were already
      torn apart.  */
@@ -1239,8 +1242,7 @@ resolve_shift_zext (rtx_insn *insn)
   src_reg_num = (GET_CODE (op) == LSHIFTRT || GET_CODE (op) == ASHIFTRT)
                ? 1 : 0;
 
-  if (WORDS_BIG_ENDIAN
-      && GET_MODE_SIZE (GET_MODE (op_operand)) > UNITS_PER_WORD)
+  if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
     src_reg_num = 1 - src_reg_num;
 
   if (GET_CODE (op) == ZERO_EXTEND)

diff --git a/gcc/optabs.c b/gcc/optabs.c
index 1dfb545d251e5bbb26cc2a753de26d7477c8b441..d9609ffc18ccd5ffdc54c06885ff249921bed5c3 100644 (file)
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -2737,22 +2737,24 @@ expand_unop (machine_mode mode, optab unoptab, rtx op0, rtx target,
     }
 
   if (unoptab == popcount_optab
-      && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD
+      && is_a <scalar_int_mode> (mode, &int_mode)
+      && GET_MODE_SIZE (int_mode) == 2 * UNITS_PER_WORD
       && optab_handler (unoptab, word_mode) != CODE_FOR_nothing
       && optimize_insn_for_speed_p ())
     {
-      temp = expand_doubleword_popcount (mode, op0, target);
+      temp = expand_doubleword_popcount (int_mode, op0, target);
       if (temp)
        return temp;
     }
 
   if (unoptab == parity_optab
-      && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD
+      && is_a <scalar_int_mode> (mode, &int_mode)
+      && GET_MODE_SIZE (int_mode) == 2 * UNITS_PER_WORD
       && (optab_handler (unoptab, word_mode) != CODE_FOR_nothing
          || optab_handler (popcount_optab, word_mode) != CODE_FOR_nothing)
       && optimize_insn_for_speed_p ())
     {
-      temp = expand_doubleword_parity (mode, op0, target);
+      temp = expand_doubleword_parity (int_mode, op0, target);
       if (temp)
        return temp;
     }