* simops.c: Treat both operands as signed values for

        "div" instruction.
Fixes another dozen c-torture execution failures.

diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index 7695f4fc7d9c06c3c0a584258e129fde1b69d450..ce0dc915a1c8cc9155f4e76b44d1d42bb0757ae2 100644 (file)
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,5 +1,16 @@
+Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * simops.c: Treat both operands as signed values for
+       "div" instruction.
+
+       * simops.c: Fix simulation of division instructions.
+       Fix typos/thinkos in several "cmp" and "sub" instructions.
+
 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
 
+       * simops.c: Fix carry bit handling in "sub" and "cmp"
+       instructions.
+
        * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
 
 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)

diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index 931da3a9af97c948eb516ada2373e7c4499bbd85..6b4fde6f4cd7ea91e494bd5cc7b0d53d43ba1bf6 100644 (file)
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -1421,8 +1421,8 @@ void OP_F260 ()
   temp = State.regs[REG_MDR];
   temp <<= 32;
   temp |= State.regs[REG_D0 + (insn & 0x3)];
-  State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
-  temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
+  State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
+  temp /= (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);