#include "sv_decode.h"
#include "processor.h"
+static int get_bitwidth(uint8_t elwidth, int xlen)
+{
+ switch (elwidth) {
+ case 0: return xlen;
+ case 1: return xlen / 2;
+ case 2: return xlen * 2;
+ default: return 8;
+ }
+}
+
sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled,
- insn_bits_t bits, unsigned int f,
+ insn_bits_t bits, unsigned int f, int xlen,
uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
uint64_t &p_sp, uint64_t *p_im,
int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
int *o_imm) :
- insn_t(bits), p(pr), sv_enabled(_sv_enabled), vloop_continue(false),
+ insn_t(bits), p(pr), src_bitwidth(0),
+ sv_enabled(_sv_enabled), vloop_continue(false),
at_least_one_reg_vectorised(false), fimap(f),
offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
offs_sp(o_sp),
prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3), psp(p_sp),
save_branch_addr(0)
{
+ // work out the source element width based on what is used
+ // note that this has to match with id_regs.py patterns
+
+ unsigned int bm=2;
+ for (int i = 1; i < 12; i++, bm<<=1)
+ {
+ sv_reg_entry* r = NULL;
+ if (bm == (REG_RS1 & fimap)) {
+ r = get_regentry(rs1(), true);
+ } else if (bm == (REG_RS2 & fimap)) {
+ r = get_regentry(rs2(), true);
+ } else if (bm == (REG_RS3 & fimap)) {
+ r = get_regentry(rs3(), true);
+ } else if (bm == (REG_RVC_RS1 & fimap)) {
+ r = get_regentry(rvc_rs1(), true);
+ } else if (bm == (REG_RVC_RS2 & fimap)) {
+ r = get_regentry(rvc_rs2(), true);
+ } else if (bm == (REG_RVC_RS1S & fimap)) {
+ r = get_regentry(rvc_rs1s(), true);
+ } else if (bm == (REG_RVC_RS2S & fimap)) {
+ r = get_regentry(rvc_rs2s(), true);
+ } else if (bm == (REG_FRS1 & fimap)) {
+ r = get_regentry(rs1(), false);
+ } else if (bm == (REG_FRS2 & fimap)) {
+ r = get_regentry(rs2(), false);
+ } else if (bm == (REG_FRS3 & fimap)) {
+ r = get_regentry(rs3(), false);
+ }
+ if (r == NULL || !r->active) {
+ continue;
+ }
+ uint8_t elwidth = r->elwidth;
+ uint8_t bitwidth = get_bitwidth(elwidth, xlen);
+ src_bitwidth = std::max(src_bitwidth, bitwidth);
+ }
}
sv_pred_entry* sv_insn_t::get_predentry(uint64_t reg, bool intreg)
#define REG_RVC_RS2 0x20
#define REG_RVC_RS1S 0x40
#define REG_RVC_RS2S 0x80
+#define REG_FRD 0x100
+#define REG_FRS1 0x200
+#define REG_FRS2 0x400
+#define REG_FRS3 0x800
class processor_t;
{
public:
sv_insn_t(processor_t *pr, bool _sv_enabled, insn_bits_t bits, unsigned int f,
+ int xlen,
uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
uint64_t &p_sp, uint64_t *p_im,
int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
bool stop_vloop(void);
processor_t *p;
+ uint8_t src_bitwidth;
bool sv_enabled;
// cached version of remap: if remap is called multiple times