rename vco_test_ana to pll_testout_o

diff --git a/libresoc/core.py b/libresoc/core.py
index 681ccf65da70d47f154cf102d801ab4b3ef1e9c6..478bcaf330cf239e4a4310de902da2d69e590220 100644 (file)
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -275,7 +275,7 @@ class LibreSoC(CPU):
             self.pll_ana_o = Signal()
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_18_o'] = self.pll_18_o
-            self.cpu_params['o_vco_test_ana'] = self.pll_ana_o
+            self.cpu_params['o_pll_testout_o'] = self.pll_ana_o
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus, True))