O3CPU: Fix a bug where stores in the cpu where never marked as split.

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index cf51f8eabc9c31c59e8da94d89c2f7ce4dca0e03..7b8b1e2e33f27ba8999a4d73c9a60d92bc4ac752 100644 (file)
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -822,6 +822,12 @@ LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
     storeQueue[store_idx].sreqLow = sreqLow;
     storeQueue[store_idx].sreqHigh = sreqHigh;
     storeQueue[store_idx].size = sizeof(T);
+
+    // Split stores can only occur in ISAs with unaligned memory accesses.  If
+    // a store request has been split, sreqLow and sreqHigh will be non-null.
+    if (TheISA::HasUnalignedMemAcc && sreqLow) {
+        storeQueue[store_idx].isSplit = true;
+    }
     assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
 
     T gData = htog(data);