Clear EVEC LSBs, which kindly prevents a segfault

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 05fee796324440de4d3fcb7b38b2d67d8bfc060a..ed19509496f6960411f0f1d1ee8ec330ea72db19 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -243,8 +243,8 @@ reg_t processor_t::set_pcr(int which, reg_t val)
     case CSR_EPC:
       state.epc = val;
       break;
-    case CSR_EVEC: 
-      state.evec = val;
+    case CSR_EVEC:
+      state.evec = val & ~3;
       break;
     case CSR_CYCLE:
     case CSR_TIME: