adjust mmu load to take reg_spec_t so that proper offset-adjustments can be made

the adding of the immediate plus the relevant offset to the relevant
register needs to be calculated before the load takes place.  algorithm
is slightly different from the one used in rv_add

diff --git a/riscv/insns/c_fld.h b/riscv/insns/c_fld.h
index 273e8c1d04c0cdf5c224d3f1b174c85d31c3b56b..5ff71094087040fd954f4faefdf7db335e796d19 100644 (file)
--- a/riscv/insns/c_fld.h
+++ b/riscv/insns/c_fld.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-WRITE_RVC_FRS2S(f64(MMU.load_uint64(rv_add(RVC_RS1S, insn.rvc_ld_imm()))));
+WRITE_RVC_FRS2S(f64(MMU.load_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm()))); //RVC_RS1S

diff --git a/riscv/insns/c_flw.h b/riscv/insns/c_flw.h
index efe1c867e6c6460b34dcb1fc18238dd486ff8f16..7e87c436b87eca11b21b15112e021cb8fc870d18 100644 (file)
--- a/riscv/insns/c_flw.h
+++ b/riscv/insns/c_flw.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  WRITE_RVC_FRS2S(f32(MMU.load_uint32(rv_add(RVC_RS1S, insn.rvc_lw_imm()))));
+  WRITE_RVC_FRS2S(f32(MMU.load_uint32(insn.rvc_rs1s(), insn.rvc_lw_imm()))); //RVC_RS1S
 } else { // c.ld
-  WRITE_RVC_RS2S(MMU.load_int64(rv_add(RVC_RS1S, insn.rvc_ld_imm())));
+  WRITE_RVC_RS2S(MMU.load_int64(insn.rvc_rs1s(), insn.rvc_ld_imm())); //RVC_RS1S
 }

diff --git a/riscv/insns/c_lw.h b/riscv/insns/c_lw.h
index d08bab56c1d880e493b167f2cc7dcb410548fdb2..40db006d7e145e7949de309e9a5b3c0cc814c93b 100644 (file)
--- a/riscv/insns/c_lw.h
+++ b/riscv/insns/c_lw.h
@@ -1,2 +1,2 @@
 require_extension('C');
-WRITE_RVC_RS2S(MMU.load_int32(rv_add(RVC_RS1S, insn.rvc_lw_imm())));
+WRITE_RVC_RS2S(MMU.load_int32(insn.rvc_rs1s(), insn.rvc_lw_imm())); // RVC_RS1S

diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
index c63fdd80498b612ffaadf16b7abcb1f7bdd4fff6..d2751298015ed3af2dce483df07670f90d7c4930 100644 (file)
--- a/riscv/insns/fld.h
+++ b/riscv/insns/fld.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(f64(MMU.load_uint64(rv_add(RS1, insn.i_imm()))));
+WRITE_FRD(f64(MMU.load_uint64(insn.rs1(), insn.i_imm()))); // RS1

diff --git a/riscv/insns/flq.h b/riscv/insns/flq.h
index 0e371ef4399de4426837426f524c6d02f98330f1..67762715b6e0380591ce4ab3dd3bc3af3478e6dd 100644 (file)
--- a/riscv/insns/flq.h
+++ b/riscv/insns/flq.h
@@ -1,3 +1,3 @@
 require_extension('Q');
 require_fp;
-WRITE_FRD(MMU.load_float128(rv_add(RS1, insn.i_imm())));
+WRITE_FRD(MMU.load_float128(rv_add(RS1, insn.i_imm()))); // XXX TODO: adjust to SV

diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index 301b9b2c0706ed7e1e562cdd0eb185e377743205..4659e4b5cb09e5ae5a4dbbf28288b94ab7b0ff0a 100644 (file)
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(f32(MMU.load_uint32(rv_add(RS1, insn.i_imm()))));
+WRITE_FRD(f32(MMU.load_uint32(insn.rs1(), insn.i_imm()))); // RS1

diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index 61e44dabffe5ec4d956bf0d85ebfdc141d9fabe4..aa5a88386543599a330c84fc1e4902a846cf13d8 100644 (file)
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_int8(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_int8(insn.rs1(), insn.i_imm())); // RS1

diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index 2165875816194747d2a9f1a44dc3230ad8769bb6..04d954a3dec116fa6c3aff2316c9cae8d66f4b71 100644 (file)
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_uint8(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_uint8(insn.rs1(), insn.i_imm())); // RS1

diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 6349603c0ccf79a38780746ae4c8532f16690617..50249be773a2e5b3fc79b11996a8a5ff713f5c42 100644 (file)
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(MMU.load_int64(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_int64(insn.rs1(), insn.i_imm())); // RS1

diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
index 0ac4b9a5b350f9e8d457d001ac69c411c41b7d37..9c44519a90e28825f7ab04b363923611f1fef47b 100644 (file)
--- a/riscv/insns/lh.h
+++ b/riscv/insns/lh.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_int16(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_int16(insn.rs1(), insn.i_imm())); // RS1

diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index b428ffaa6ea2d1690bb86034e35ef19727380d88..8d5167b5b5a0498845934c0610aaeeb77458c4f6 100644 (file)
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_uint16(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_uint16(insn.rs1(), insn.i_imm())); // RS1

diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 45e082a6f7fe2ebc66cbbfc7c727495c0100d9ad..d33625fd8270b5923524d66102a9e7ce4c6d91ea 100644 (file)
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_int32(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_int32(insn.rs1(), insn.i_imm())); // RS1

diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index f0e46a2a02c7799054d1c08f8c85fa59cc6ae2b4..bde9c07735379a95b1cae59a4aefc15d6bbd903d 100644 (file)
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(MMU.load_uint32(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_uint32(insn.rs1(), insn.i_imm())); // RS1

diff --git a/riscv/sv_mmu.cc b/riscv/sv_mmu.cc
index fa2065158c9e5199d9c6a29380cc5bdbf9f87af4..829e39f46f3e880fe37e3e9d921fccada31a9c02 100644 (file)
--- a/riscv/sv_mmu.cc
+++ b/riscv/sv_mmu.cc
@@ -1,6 +1,12 @@
 #include "sv_mmu.h"
 
 #define sv_load_func(type, ext) \
+sv_reg_t sv_mmu_t::load_##type(reg_spec_t const& spec, sv_reg_t const& offs) { \
+  reg_t reg = proc->s.READ_REG(spec); \
+  sv_reg_t addr = proc->s.rv_add(reg, offs); \
+  type##_t v = mmu_t::load_##type(addr); \
+  return proc->s.adjust_load(sv_reg_t(v), sizeof(type##_t), ext); \
+} \
 sv_reg_t sv_mmu_t::load_##type(reg_t const& addr) { \
   type##_t v = mmu_t::load_##type(addr); \
   return proc->s.adjust_load(sv_reg_t(v), sizeof(type##_t), ext); \

diff --git a/riscv/sv_mmu.h b/riscv/sv_mmu.h
index 7101ba4793dc4220f9ec12816cc317accbf5616c..824d166976b472dd34fafc9996d7c0ca68933e16 100644 (file)
--- a/riscv/sv_mmu.h
+++ b/riscv/sv_mmu.h
@@ -13,6 +13,7 @@ public:
   sv_mmu_t(simif_t* sim, processor_t* proc) : mmu_t(sim, proc) {}
 
   #define sv_load_func_decl(type) \
+    sv_reg_t load_##type(reg_spec_t const& reg, sv_reg_t const& offs); \
     sv_reg_t load_##type(reg_t const& addr);
 
   // load value from memory at aligned address; zero extend to register width