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Added brackets for lhzx instruction
authorShriya Sharma <shriya@redsemiconductor.com>
Tue, 26 Sep 2023 11:02:17 +0000 (12:02 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 22 Dec 2023 19:26:21 +0000 (19:26 +0000)
openpower/isa/fixedload.mdwn patch | blob | history

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 649fa04cfced102b79645d672f85445ed194d512..30bcb3ef64167479afbbfaeeb61e5aa7eea143ea 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -160,7 +160,7 @@ Description:
 
     Let the effective address (EA) be the sum
     (RA|0)+ (RB). The halfword in storage addressed by
-    EA is loaded into RT 48:63. RT 0:47 are set to 0.
+    EA is loaded into RT[48:63]. RT 0:47 are set to 0.
 
 Special Registers Altered: