+2014-08-25 David Malcolm <dmalcolm@redhat.com>
+
+ * config/tilepro/tilepro-protos.h (tilepro_output_cbranch_with_opcode):
+ Strengthen param 1 from rtx to rtx_insn *.
+ (tilepro_output_cbranch): Likewise.
+ (tilepro_adjust_insn_length): Likewise.
+ (tilepro_final_prescan_insn): Likewise for sole param.
+
+ * config/tilepro/tilepro.c (tilepro_legitimize_tls_address):
+ Likewise for local "last".
+ (cbranch_predicted_p): Likewise for param "insn".
+ (tilepro_output_simple_cbranch_with_opcode): Likewise.
+ (tilepro_output_cbranch_with_opcode): Likewise.
+ (tilepro_output_cbranch): Likewise.
+ (frame_emit_load): Likewise for return type and locals "seq",
+ "insn".
+ (emit_sp_adjust): Likewise for return type and local "insn".
+ (tilepro_expand_epilogue): Likewise for locals "last_insn",
+ "insn".
+ (tilepro_adjust_insn_length): Likewise for param "insn".
+ (next_insn_to_bundle): Likewise for return type and params
+ "r", "end".
+ (tilepro_gen_bundles): Likewise for locals "insn", "next", "end".
+ (replace_pc_relative_symbol_ref): Likewise for param "insn" and
+ local "new_insns".
+ (match_addli_pcrel): Likewise for param "insn".
+ (replace_addli_pcrel): Likewise.
+ (match_auli_pcrel): Likewise.
+ (replace_auli_pcrel): Likewise.
+ (tilepro_fixup_pcrel_references): Likewise for locals "insn",
+ "next_insn".
+ (reorder_var_tracking_notes): Likewise for locals "insn", "next",
+ "queue", "next_queue", "prev".
+ (tilepro_asm_output_mi_thunk): Likewise for local "insn".
+ (tilepro_final_prescan_insn): Likewise for param "insn".
+
2014-08-25 David Malcolm <dmalcolm@redhat.com>
* config/tilegx/tilegx-protos.h (tilegx_output_cbranch_with_opcode):
extern bool tilepro_emit_setcc (rtx[], enum machine_mode);
extern void tilepro_emit_conditional_branch (rtx[], enum machine_mode);
extern rtx tilepro_emit_conditional_move (rtx);
-extern const char *tilepro_output_cbranch_with_opcode (rtx, rtx *,
+extern const char *tilepro_output_cbranch_with_opcode (rtx_insn *, rtx *,
const char *,
const char *, int,
bool);
-extern const char *tilepro_output_cbranch (rtx, rtx *, bool);
+extern const char *tilepro_output_cbranch (rtx_insn *, rtx *, bool);
extern void tilepro_expand_tablejump (rtx, rtx);
extern void tilepro_expand_builtin_vector_binop (rtx (*)(rtx, rtx, rtx),
enum machine_mode, rtx,
extern int tilepro_initial_elimination_offset (int, int);
extern rtx tilepro_return_addr (int, rtx);
extern rtx tilepro_eh_return_handler_rtx (void);
-extern int tilepro_adjust_insn_length (rtx, int);
+extern int tilepro_adjust_insn_length (rtx_insn *, int);
extern int tilepro_asm_preferred_eh_data_format (int, int);
-extern void tilepro_final_prescan_insn (rtx);
+extern void tilepro_final_prescan_insn (rtx_insn *);
extern const char *tilepro_asm_output_opcode (FILE *, const char *);
extern void tilepro_function_profiler (FILE *, int);
case TLS_MODEL_GLOBAL_DYNAMIC:
case TLS_MODEL_LOCAL_DYNAMIC:
{
- rtx r0, temp1, temp2, temp3, got, last;
+ rtx r0, temp1, temp2, temp3, got;
+ rtx_insn *last;
ret = gen_reg_rtx (Pmode);
r0 = gen_rtx_REG (Pmode, 0);
}
case TLS_MODEL_INITIAL_EXEC:
{
- rtx temp1, temp2, temp3, got, last;
+ rtx temp1, temp2, temp3, got;
+ rtx_insn *last;
ret = gen_reg_rtx (Pmode);
temp1 = gen_reg_rtx (Pmode);
}
case TLS_MODEL_LOCAL_EXEC:
{
- rtx temp1, last;
+ rtx temp1;
+ rtx_insn *last;
ret = gen_reg_rtx (Pmode);
temp1 = gen_reg_rtx (Pmode);
/* Return true if INSN is annotated with a REG_BR_PROB note that
indicates it's a branch that's predicted taken. */
static bool
-cbranch_predicted_p (rtx insn)
+cbranch_predicted_p (rtx_insn *insn)
{
rtx x = find_reg_note (insn, REG_BR_PROB, 0);
/* Output assembly code for a specific branch instruction, appending
the branch prediction flag to the opcode if appropriate. */
static const char *
-tilepro_output_simple_cbranch_with_opcode (rtx insn, const char *opcode,
+tilepro_output_simple_cbranch_with_opcode (rtx_insn *insn, const char *opcode,
int regop, bool netreg_p,
bool reverse_predicted)
{
/* Output assembly code for a specific branch instruction, appending
the branch prediction flag to the opcode if appropriate. */
const char *
-tilepro_output_cbranch_with_opcode (rtx insn, rtx *operands,
+tilepro_output_cbranch_with_opcode (rtx_insn *insn, rtx *operands,
const char *opcode,
const char *rev_opcode,
int regop, bool netreg_p)
/* Output assembly code for a conditional branch instruction. */
const char *
-tilepro_output_cbranch (rtx insn, rtx *operands, bool reversed)
+tilepro_output_cbranch (rtx_insn *insn, rtx *operands, bool reversed)
{
enum rtx_code code = GET_CODE (operands[1]);
const char *opcode;
/* Emit a load in the stack frame to load REGNO from address ADDR.
Add a REG_CFA_RESTORE note to CFA_RESTORES if CFA_RESTORES is
non-null. Return the emitted insn. */
-static rtx
+static rtx_insn *
frame_emit_load (int regno, rtx addr, rtx *cfa_restores)
{
rtx reg = gen_rtx_REG (Pmode, regno);
/* Helper function to set RTX_FRAME_RELATED_P on instructions,
including sequences. */
-static rtx
+static rtx_insn *
set_frame_related_p (void)
{
- rtx seq = get_insns ();
- rtx insn;
+ rtx_insn *seq = get_insns ();
+ rtx_insn *insn;
end_sequence ();
if (!seq)
- return NULL_RTX;
+ return NULL;
if (INSN_P (seq))
{
large register and using 'add'.
This happens after reload, so we need to expand it ourselves. */
-static rtx
+static rtx_insn *
emit_sp_adjust (int offset, int *next_scratch_regno, bool frame_related,
rtx reg_notes)
{
rtx to_add;
rtx imm_rtx = gen_int_si (offset);
- rtx insn;
+ rtx_insn *insn;
if (satisfies_constraint_J (imm_rtx))
{
/* We can add this using a single addi or addli. */
rtx reg_save_addr[ROUND_ROBIN_SIZE] = {
NULL_RTX, NULL_RTX, NULL_RTX, NULL_RTX
};
- rtx last_insn, insn;
+ rtx_insn *last_insn, *insn;
unsigned int which_scratch;
int offset, start_offset, regno;
rtx cfa_restores = NULL_RTX;
by attributes in the machine-description file. This is where we
account for bundles. */
int
-tilepro_adjust_insn_length (rtx insn, int length)
+tilepro_adjust_insn_length (rtx_insn *insn, int length)
{
enum machine_mode mode = GET_MODE (insn);
/* Skip over irrelevant NOTEs and such and look for the next insn we
would consider bundling. */
-static rtx
-next_insn_to_bundle (rtx r, rtx end)
+static rtx_insn *
+next_insn_to_bundle (rtx_insn *r, rtx_insn *end)
{
for (; r != end; r = NEXT_INSN (r))
{
return r;
}
- return NULL_RTX;
+ return NULL;
}
basic_block bb;
FOR_EACH_BB_FN (bb, cfun)
{
- rtx insn, next;
- rtx end = NEXT_INSN (BB_END (bb));
+ rtx_insn *insn, *next;
+ rtx_insn *end = NEXT_INSN (BB_END (bb));
for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next)
{
/* Helper function for tilepro_fixup_pcrel_references. */
static void
-replace_pc_relative_symbol_ref (rtx insn, rtx opnds[4], bool first_insn_p)
+replace_pc_relative_symbol_ref (rtx_insn *insn, rtx opnds[4], bool first_insn_p)
{
- rtx new_insns;
+ rtx_insn *new_insns;
start_sequence ();
/* Returns whether INSN is a pc-relative addli insn. */
static bool
-match_addli_pcrel (rtx insn)
+match_addli_pcrel (rtx_insn *insn)
{
rtx pattern = PATTERN (insn);
rtx unspec;
/* Helper function for tilepro_fixup_pcrel_references. */
static void
-replace_addli_pcrel (rtx insn)
+replace_addli_pcrel (rtx_insn *insn)
{
rtx pattern = PATTERN (insn);
rtx set_src;
/* Returns whether INSN is a pc-relative auli insn. */
static bool
-match_auli_pcrel (rtx insn)
+match_auli_pcrel (rtx_insn *insn)
{
rtx pattern = PATTERN (insn);
rtx high;
/* Helper function for tilepro_fixup_pcrel_references. */
static void
-replace_auli_pcrel (rtx insn)
+replace_auli_pcrel (rtx_insn *insn)
{
rtx pattern = PATTERN (insn);
rtx set_src;
static void
tilepro_fixup_pcrel_references (void)
{
- rtx insn, next_insn;
+ rtx_insn *insn, *next_insn;
bool same_section_as_entry = true;
for (insn = get_insns (); insn; insn = next_insn)
basic_block bb;
FOR_EACH_BB_FN (bb, cfun)
{
- rtx insn, next;
- rtx queue = NULL_RTX;
+ rtx_insn *insn, *next;
+ rtx_insn *queue = NULL;
bool in_bundle = false;
for (insn = BB_HEAD (bb); insn != BB_END (bb); insn = next)
{
while (queue)
{
- rtx next_queue = PREV_INSN (queue);
+ rtx_insn *next_queue = PREV_INSN (queue);
SET_PREV_INSN (NEXT_INSN (insn)) = queue;
SET_NEXT_INSN (queue) = NEXT_INSN (insn);
SET_NEXT_INSN (insn) = queue;
{
if (in_bundle)
{
- rtx prev = PREV_INSN (insn);
+ rtx_insn *prev = PREV_INSN (insn);
SET_PREV_INSN (next) = prev;
SET_NEXT_INSN (prev) = next;
HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
tree function)
{
- rtx this_rtx, insn, funexp;
+ rtx this_rtx, funexp;
+ rtx_insn *insn;
/* Pretend to be a post-reload pass while generating rtl. */
reload_completed = 1;
/* Implement FINAL_PRESCAN_INSN. This is used to emit bundles. */
void
-tilepro_final_prescan_insn (rtx insn)
+tilepro_final_prescan_insn (rtx_insn *insn)
{
/* Record this for tilepro_asm_output_opcode to examine. */
insn_mode = GET_MODE (insn);
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