Remove need for $currQ port connection

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 52273e9b92cbde335764c7798e8e5141e40f75a3..65792421f570fb7e3e8a344f7f466908de9a7cf9 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -483,12 +483,12 @@ struct XAigerWriter
 
                                if (box_module->get_bool_attribute("\\abc9_flop")) {
                                        IdString port_name = "\\$currQ";
-                                       RTLIL::Wire* w = box_module->wire(port_name);
-                                       SigSpec rhs = cell->getPort(port_name);
+                                       Wire *w = box_module->wire(port_name);
+                                       SigSpec rhs = module->wire(stringf("%s.$currQ", cell->name.c_str()));
                                        log_assert(GetSize(w) == GetSize(rhs));
 
                                        int offset = 0;
-                                       for (auto b : rhs.bits()) {
+                                       for (auto b : rhs) {
                                                SigBit I = sigmap(b);
                                                if (b == RTLIL::Sx)
                                                        b = State::S0;

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 08a1af2d553188365e72bf11170b14b1fd54440e..c2dc9b959533539a72eddb8a7f31f4bea1f4606b 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -256,6 +256,14 @@ struct TechmapWorker
                                if (w->attributes.count(ID(src)))
                                        w->add_strpool_attribute(ID(src), extra_src_attrs);
                        }
+
+
+                       if (it.second->name.begins_with("\\_TECHMAP_REPLACE_")) {
+                               IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
+                               Wire *replace_w = module->addWire(replace_name, it.second);
+                               module->connect(replace_w, w);
+                       }
+
                        design->select(module, w);
                }
 

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 6a0e18abe0f95f42983a722f226e0dbcf2e81062..4eec77df97e14129d2151083ae25c3b12ed77093 100644 (file)
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -33,34 +33,35 @@
 //   behaviour) with:
 // (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9
 //     the location of its basic D-Q flop
-// (b) a special \$currQ connection that feeds back into the (combinatorial)
-//     FD* cell to facilitate clock-enable behaviour -- note that \$currQ
-//     isn't a real input port, it is one that is understood only by abc9
+// (b) a special TECHMAP_REPLACE_.$currQwire that will be used for feedback
+//     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
-  wire \$nextQ ;
+  wire $nextQ;
   FDRE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_R_INVERTED(IS_R_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
-  wire \$nextQ ;
+  wire $nextQ;
   FDRE_1 #(
     .INIT(|0),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
 endmodule
 
 module FDCE (output reg Q, input C, CE, D, CLR);
@@ -68,28 +69,30 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire \$nextQ , \$currQ ;
+  wire $currQ, $nextQ;
   FDCE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_CLR_INVERTED(IS_CLR_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR)
+    .D(D), .Q($nextQ),  .C(C), .CE(CE), .CLR(CLR)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
-  wire \$nextQ , \$currQ ;
+  wire $nextQ, $currQ;
   FDCE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
 endmodule
 
 module FDPE (output reg Q, input C, CE, D, PRE);
@@ -97,28 +100,30 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire \$nextQ , \$currQ ;
+  wire $nextQ, $currQ;
   FDPE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_PRE_INVERTED(IS_PRE_INVERTED),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
-  wire \$nextQ , \$currQ ;
+  wire $nextQ, $currQ;
   FDPE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
@@ -126,26 +131,28 @@ module FDSE (output reg Q, input C, CE, D, S);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
-  wire \$nextQ ;
+  wire $nextQ;
   FDSE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_S_INVERTED(IS_S_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b0;
-  wire \$nextQ ;
+  wire $nextQ;
   FDSE_1 #(
     .INIT(|0),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
 endmodule
 
 module RAM32X1D (

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 3aa686e81764570588a22cea1162fd6ff7184604..7ab28b0aaf023678aecaa29fbd6f6e126a87856e 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -258,31 +258,31 @@ module FDRE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
 
   // Special signal indicating clock domain
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
+  assign $currQ = Q;
   generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) Q <= \$nextQ ;
-    1'b1: always @(negedge C) Q <= \$nextQ ;
+    1'b0: always @(posedge C) Q <= $nextQ;
+    1'b1: always @(negedge C) Q <= $nextQ;
   endcase endgenerate
 `endif
 endmodule
@@ -297,29 +297,29 @@ module FDRE_1 (
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
 
   // Special signal indicating clock domain
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
-  always @(negedge C) Q <= \$nextQ ;
+  assign $currQ = Q;
+  always @(negedge C) Q <= $nextQ;
 `endif
 endmodule
 
@@ -341,15 +341,15 @@ module FDCE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
   // Since this is an async flop, async behaviour is also dealt with
   //   using the $_ABC_ASYNC box by abc_map.v
 
@@ -357,19 +357,19 @@ module FDCE (
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
+  assign $currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
-    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
-    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
-    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
-    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
+    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ;
+    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ;
+    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ;
+    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ;
   endcase endgenerate
 `endif
 endmodule
@@ -384,15 +384,15 @@ module FDCE_1 (
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (CE) Q <= D; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
   // Since this is an async flop, async behaviour is also dealt with
   //   using the $_ABC_ASYNC box by abc_map.v
 
@@ -400,15 +400,15 @@ module FDCE_1 (
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
-  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
+  assign $currQ = Q;
+  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= $nextQ;
 `endif
 endmodule
 
@@ -430,15 +430,15 @@ module FDPE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
   // Since this is an async flop, async behaviour is also dealt with
   //   using the $_ABC_ASYNC box by abc_map.v
 
@@ -446,19 +446,19 @@ module FDPE (
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
+  assign $currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
-    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
-    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
-    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
-    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
+    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ;
+    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ;
+    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ;
+    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ;
   endcase endgenerate
 `endif
 endmodule
@@ -473,15 +473,15 @@ module FDPE_1 (
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (CE) Q <= D; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
   // Since this is an async flop, async behaviour is also dealt with
   //   using the $_ABC_ASYNC box by abc_map.v
 
@@ -489,15 +489,15 @@ module FDPE_1 (
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
-  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
+  assign $currQ = Q;
+  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= $nextQ;
 `endif
 endmodule
 
@@ -519,31 +519,31 @@ module FDSE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
 
   // Special signal indicating clock domain
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
+  assign $currQ = Q;
   generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) Q <= \$nextQ ;
-    1'b1: always @(negedge C) Q <= \$nextQ ;
+    1'b0: always @(posedge C) Q <= $nextQ;
+    1'b1: always @(negedge C) Q <= $nextQ;
   endcase endgenerate
 `endif
 endmodule
@@ -558,29 +558,29 @@ module FDSE_1 (
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
 
   // Special signal indicating clock domain
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
-  always @(negedge C) Q <= \$nextQ ;
+  assign $currQ = Q;
+  always @(negedge C) Q <= $nextQ;
 `endif
 endmodule