spelling correction

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 0ce4b0215722553b80262282dd7b41d0bf4dcbc0..0909e3fff67ee2a9ef30214d16ed3f195e644148 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -948,7 +948,7 @@ Branch operations use standard RV opcodes that are reinterpreted to
 be "predicate variants" in the instance where either of the two src
 registers are marked as vectors (active=1, vector=1).
 
-Note that he predication register to use (if one is enabled) is taken from
+Note that the predication register to use (if one is enabled) is taken from
 the *first* src register.  The target (destination) predication register
 to use (if one is enabled) is taken from the *second* src register.