Makefile.in: Add gen-zero-r0 option.

sim-main.h (GPR_SET, GPR_CLEAR): Define.
simops.c (OP_24007E0):  Sign extend the imm9 operand of a mul instruction.

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index cb20ad5f8645ad7ad6b76554a3492132a20cbf68..c8b3aabdc4af2d1c3ef171385cf10e9f8f446e61 100644 (file)
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,12 @@
+2002-08-29  Nick Clifton  <nickc@redhat.com>
+
+       From 2001-08-23  Catherine Moore  <clm@redhat.com>
+
+       * Makefile.in: Add gen-zero-r0 option.
+       * sim-main.h (GPR_SET, GPR_CLEAR): Define.
+       * simops.c (OP_24007E0):  Sign extend the imm9
+       operand of a mul instruction.
+
 2002-06-17  Andrew Cagney  <cagney@redhat.com>
 
        * simops.c (trace_result): Fix printf formatting.

diff --git a/sim/v850/Makefile.in b/sim/v850/Makefile.in
index 110cb1761f95ab3a17dc9743a2702a660a85a3a4..89029d6a627050a0679d15843a36443cb9169d81 100644 (file)
--- a/sim/v850/Makefile.in
+++ b/sim/v850/Makefile.in
@@ -82,6 +82,7 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen
        ../igen/igen \
                $(IGEN_TRACE) \
                -G gen-direct-access \
+               -G gen-zero-r0 \
                -i $(IGEN_INSN) \
                -o $(IGEN_DC) \
                -x \

diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index 37ea31f3f4c533a6c9239d66d0fd8773e3a92eef..a16ec00a699b88eac2ae6ecef00bc8db61739137 100644 (file)
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -366,6 +366,8 @@ do { \
 
 #endif
 
+#define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
+#define GPR_CLEAR(N)    (State.regs[(N)] = 0)
 
 extern void divun ( unsigned int       N,
                    unsigned long int  als,

diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 9a83d0796a2cabd2845c863e70933555542c865c..d8a4d58ae11334c3d3ca53b4c62cdfd23d8d9e7a 100644 (file)
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -2458,7 +2458,7 @@ OP_24007E0 (void)
 {
   trace_input ("mul", OP_IMM_REG_REG, 0);
 
-  Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
+  Multiply64 (true, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)));
 
   trace_output (OP_IMM_REG_REG);